參數(shù)資料
型號: T89C51CC01UA-RLTIM
廠商: Atmel
文件頁數(shù): 28/123頁
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
標(biāo)準(zhǔn)包裝: 160
系列: AT89C CAN
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: AT89STK-06-ND - KIT DEMOBOARD 8051 MCU W/CAN
其它名稱: T89C51CC01UARLTIM
2010 Microchip Technology Inc.
DS41303G-page 123
PIC18F2XK20/4XK20
TABLE 10-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
OSC1/CLKIN/RA7
RA7
0
O
DIG
LATA<7> data output. Disabled in external oscillator modes.
1
I
TTL
PORTA<7> data input. Disabled in external oscillator modes.
OSC1
x
I
ANA
Main oscillator input connection.
CLKIN
x
I
ANA
Main clock input connection.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTA
RA7(1)
RA6(1)
RA5
RA4
RA3
RA2
RA1
RA0
LATA
LATA7(1)
LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch)
TRISA
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
ANSEL
ANS7(2)
ANS6(2)
ANS5(2)
ANS4
ANS3
ANS2
ANS1
ANS0
SLRCON
SLRE(2)
SLRD(2)
SLRC
SLRB
SLRA
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
2:
Not implemented on PIC18F2XK20 devices.
TABLE 10-1:
PORTA I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
Type
Description
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
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