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參數(shù)資料
| 型號： | T8536B |
| 元件分類： | Codec |
| 英文描述： | T8535B/T8536B Quad Programmable Codec |
| 中文描述： | T8535B/T8536B四可編程編解碼器 |
| 文件頁數(shù)： | 18/50頁 |
| 文件大小： | 929K |
| 代理商： | T8536B |
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18
Agere Systems Inc.
Preliminary Data Sheet
September 2001
T8535B/T8536B Quad Programmable Codec
Functional Description
(continued)
The Control Interface
(continued)
Read Command
The normal flow of information to the master controller is always in response to a read command. All control mem-
ory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from
the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting
on the serial interface line at any one time. The master controller also must ensure that the CS lead goes high after
transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case,
it should be noted that the device expects that the second time CS goes low the data is to be sent to the master;
thus, it does not interpret the DI lead as containing a valid instruction during that CS excursion and a write during
this time is not recommended. Note also that the CS lead must allow the number of bytes sent in a read command
to be transferred before a subsequent command can be received by the codec. Figures 12—15 illustrate normal or
byte-by-byte operation with continuous or gapped DCLKs. Like a write command, transitions, not frequency, are
critical with regard to gapped DCLK operation.
0079B
* Provides sufficient wait time to access read data.
Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 12. Read Operation, Normal Mode (Continuous DCLK)
COMMAND FRAME
0
1
7
0
1
7
CS
DCLK
DI
COMMAND
START ADDRESS
DATA
0
1
7
0
1
7
0
1
7
LENGTH
0
1
7
0
1
7
0
1
7
DO
WAIT
≥
1.5
μ
s
*
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