參數(shù)資料
型號(hào)： T8534
英文描述： T8533/34 Quad Programmable Line Card Signal Processor
中文描述： T8533/34四線卡可編程信號(hào)處理器
文件頁數(shù)： 44/48頁
文件大?。?/td> 890K
代理商： T8534
Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
44
Agere Systems Inc.
Applications
The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac
parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.
12-3534.z (F)
*R
VFxI
is required for complex terminations. Optional for resistive terminations.
Figure 24. POTS Interface
V
BAT1
BGND
V
BAT2
V
CC
AGND
ICM
TRGDET
ground key
not used
C
BAT1
0.1
μ
F
C
BAT2
0.1
μ
F
C
CC
0.1
μ
F
RTFLT
DCOUT
PR
PT
OVH
V
PROG
V
REF
C
RT
0.1
μ
F
R
RT
383
k
AGERE
L7591
50
V
BAT1
FUSIBLE OR PTC
50
CF1
CF2
rate of battery
reversal not
ramped
FB1 FB2 NSTAT BR
B2 B1 B0
C
F1
0.22
μ
F
C
F2
0.1
μ
F
PPM
0.5 Vrms
C
10 nF
RING
IN
PPM
IN
VITR
RCVP
RCVN
ITR
VTX
TXI
R
4750
V
BAT1
D
BAT1
V
BAT2
V
CC
C
TX
0.1
μ
F
C
0.47
μ
F
FROM
PROGRAMMABLE
D/A VOLTAGE
SOURCE
C
C1
0.1
μ
F
PCM
HIGHWAY
DX0
DR0
DX1
DR1
FS
BCLK
DGND
V
DD
SYNC
AND
CLOCK
V
DD
VFXI
VFROP
VFRON
SLIC4a
SLIC3a
SLIC2a
SLIC1a
SLIC0a
L9215G
FROM/TO
CONTROL
B2
B1
BR
NSTAT
B0
FUSIBLE OR PTC
T8534
R
P
1
R
*
20 M
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