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參數(shù)資料
| 型號： | T8534 |
| 英文描述： | T8533/34 Quad Programmable Line Card Signal Processor |
| 中文描述： | T8533/34四線卡可編程信號處理器 |
| 文件頁數(shù)： | 35/48頁 |
| 文件大小： | 890K |
| 代理商： | T8534 |
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Preliminary Data Sheet
July 2001
Signal Processor
T8533/34 Quad Programmable Line Card
Agere Systems Inc.
35
Timing Characteristics
(continued)
Table 15. Timing Characteristics
(continued)
* PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with
the rising edge of BCLK within 10 ns.
The t
SXBDLY
delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.
Table 16. Echo Canceller Characteristics
Symbol
t
IDHOLD
Parameter
Test Conditions
PCM clock frequency
= 16.384 MHz
PCM clock frequency
= 16.384 MHz
Serial clock frequency
= 4.096 MHz, PCM
clock frequency =
16.384 MHz
Serial clock frequency
= 4.096 MHz, PCM
clock frequency =
16.384 MHz
I
L
= 15 mA,
C
LOAD
= 100 pF
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Serial clock frequency
= 4.096 MHz
Min
4
Typ
—
Max
—
Unit
ns
PCM Bus Input Data Hold Time
t
IDSETUP
PCM Bus Input Data Setup
Time
Clock Edge Rise Time
7
—
—
ns
t
RISE
—
—
8
ns
t
FALL
Clock Edge Fall Time
—
—
8
ns
t
RISE
,
t
FALL
t
CSBHOLD
Line Driver Rise/Fall Time (DO
and DX outputs)
Chip Select Hold Time, Byte-by-
Byte Mode
Serial Bus Output Data Delay,
Byte-by-Byte Mode
Chip Select Setup Time, Byte-
by-Byte Mode
Serial Bus Data Hold Time,
Byte-by-Byte Mode
Serial Bus Data Setup Time,
Byte-by-Byte Mode
Chip Select Hold Time, Byte-by-
Byte Mode
—
—
30
ns
4
—
—
ns
t
SXBDLY
—
—
9
ns
t
CSBSETUP
7
—
—
ns
t
SDBHOLD
4
—
—
ns
t
SDBSETUP
7
—
—
ns
t
CSBHOLD
4
—
—
ns
Parameter
Echo Return Loss
Convergence Time
Symbol
—
—
Test Conditions
—
—
Min
—
—
Typ
45
100+
Max
—
—
Unit
dB
dB/s
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