參數(shù)資料
型號(hào)： T7288
廠(chǎng)商： Lineage Power
英文描述： CEPT/E1 Line Interface(CEPT/E1 線(xiàn)接口)
中文描述： CEPT/E1線(xiàn)路接口（CEPT/E1線(xiàn)接口）
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 432K
代理商： T7288
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
8
Lucent Technologies Inc.
Overview
(continued)
Receive Converter
The receive converter accepts bipolar input signals
(T1, R1), with a maximum of 6 dB loss at 1024 kHz,
through the interconnection cable. The received signal
is rectified while the amplitude and rise time are
restored. These input signals are peak-detected and
sliced by the receiver front end, producing the digital
signals PDATA and NDATA (see Figure 6). Receive
decision levels are automatically adjusted to be 50% of
peak-to-zero signal levels. The timing is extracted by
means of PLL circuitry that locks an internal, free-
running, current-controlled oscillator (ICO) to the
2.048 MHz component.
The PLL employs a 3-state phase detector and a low-
voltage/temperature coefficient ICO. The ICO free-
running frequency is trimmed to within
data rate at wafer probe, with V
DD
= 5.0 V and
T
A
= 25
°
C. For all operating conditions, the free-run-
ning oscillator frequency deviates from the data rate by
less than
±
7%, alleviating the problem of harmonic
lock.
±
2.5% of the
For robust operation, the PLL is augmented with a fre-
quency-acquisition capability. This feature detects if the
recovered PLL clock (RCLK) deviates by more than
+1.7%/–1.6% in frequency from a 2.048 MHz reference
clock, which must be provided at BCLK. If the RCLK
frequency is not within the prescribed range of the
BCLK frequency, the T7288 device enters a training
mode in which receive input data is disconnected from
the PLL, and the RCLK frequency is steered to equal
the BCLK frequency. After frequency acquisition is
completed, the PLL reconnects to receive input data to
acquire proper phase-lock and timing of RCLK with
respect to the incoming T1, R1 data. Valid data is avail-
able when proper phase-lock has been achieved.
The frequency acquisition circuitry is intended to avoid
improper harmonic locking during start-up situations,
such as powerup or data interruption. Once the T7288
device is phase-locked to data, the frequency-acquisi-
tion mode will not be activated.
A continuously present (i.e., ungapped, unswitched)
2.048 MHz reference clock must be present at BCLK to
enable the frequency-acquisition circuitry. However, the
receive PLL will operate even in the absence of a
2.048 MHz clock at BCLK. The 2.048 MHz clock at
TCLK can also be used to provide the 2.048 MHz refer-
ence at BCLK.
Because the clock output of the receive converter is
derived from the ICO, a free-running clock can be
present at the output of the receive converter without
data being present at the input. A shutdown pin (SD) is
provided to block this clock, if desired, to eliminate the
free-running clock upon loss of the input signal.
Both analog and digital methods of loss-of-signal
detection are used in the T7288 device. The analog sig-
nal detector shown in Figure 6 uses the output of the
receiver peak detector to determine if a signal is
present at T1 and R1. If the input amplitude drops
below 0.25 V, typical, the analog detector output
becomes active. Analog loss of signal is registered, at
most, several milliseconds after a drop in signal level,
depending on a variety of factors, such as initial signal
amplitude. Hysteresis (140 mV, typical) is provided in
the analog detector to eliminate
LOS
chattering. The
digital signal detector counts 0s in the recovered data.
If more than 32 consecutive 0s occur, the digital signal
detector becomes active. In normal operation, the
detector outputs are ORed together to form
LOS
; how-
ever, in loopback 1, only the digital signal detector is
used to monitor the looped signal. Table 3 describes
the operation of the shutdown,
LOS
, and
LOC
functions
in normal operation and in loopback 1.
The PLL is designed to accommodate large amounts of
input jitter with high power supply rejection for opera-
tion in noisy environments. Low jitter sensitivity to
power supply noise allows compact line-card layouts
that employ many line interfaces on one board. The
minimum input jitter tolerance, as specified in ITU-T
specification G.823, and the measured T7288 device
jitter tolerance are shown in Figure 7. Receiver specifi-
cations are shown in Table 11. The T7288 device satis-
fies the ITU-T jitter transfer function requirement of
recommendations G.735—G.739 (see Figure 8).
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