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參數(shù)資料
| 型號： | T7288 |
| 廠商： | Lineage Power |
| 英文描述： | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| 中文描述： | CEPT/E1線路接口（CEPT/E1線接口） |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 432K |
| 代理商： | T7288 |
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
3
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
9
Symbol
LP1
Type
I
Name/Function
This pin is cleared for a full local loopback
Loopback 1 Enable (Active-Low).
(transmit converter output to receive converter input). Most of the transmit and
receive analog circuitry is exercised in this loopback (internal pull-up is included).
Loopback 2 Enable (Active-Low).
This pin is cleared for a remote loopback. In
loopback 2, a high on TBC (pin 14) inserts the blue signal (AIS) on the transmit
side (internal pull-up is included).
Loopback 3 Enable (Active-Low).
This pin is cleared for a digital local loop-
back. Only the transmit and receive digital sections are exercised in this loopback
(internal pull-up is included).
Alarm Test Enable (Active-Low).
This pin is cleared, forcing
LOC
= 0, and VIO = 1 for testing without affecting data transmission (internal pull-
up is included).
Receive Blue Control.
This pin is set to insert the blue signal (AIS) on the
receive side (internal pull-down is included).
Transmit Blue Control.
This pin is set to insert the blue signal (AIS) on the
transmit side. This control has priority over a loopback 2 if both are operated
(internal pull-down is included).
Blue Clock.
Blue clock (AIS) input signal (2.048 MHz
be independent of the transmit clock.
Single-Rail (Active-Low)/Dual-Rail Operation.
down is included), single-rail operation is selected; if
tion is selected (see Tables 4—6).
Framer Logic Mode.
If FLM = 0 (internal pull-down is included), logic mode 1
operation occurs. If FLM = 1, logic mode 2 operation occurs (see Tables 4—6).
No Connection.
Test pin for manufacturing purposes only. This pin must be left
floating or tied to GND
D
.
Digital Ground.
Transmit Bipolar Ring.
Negative bipolar transmit output.
5 V Digital Supply (
±
10%).
Transmit Bipolar Tip.
Positive bipolar transmit output.
Impedance Select.
This pin is cleared for 75
for 120
shielded twisted-pair operation (internal pull-down is included).
5 V Analog Supply (
±
10%).
Analog Ground.
Shutdown Enable.
If this pin is high, a loss-of-signal detection (
LOC
low and causes the following (see Table 4):
For single-rail operation: RCLK high, RDATA low.
For dual-rail, logic mode 1 operation: RCLK high, RPDATA and RNDATA low.
For dual-rail, logic mode 2 operation: RCLK low, RPDATA and RNDATA high
(internal pull-down included).
Receive Bipolar Ring.
Negative bipolar receive input.
Receive Bipolar Tip.
Positive bipolar receive input.
10
LP2
I
11
LP3
I
12
ALMT
I
LOS
= 0,
13
RBC
I
14
TBC
I
15
BCLK
I
±
80 ppm). This clock can
16
SR
/DR
I
If
SR
/DR = 0 (internal pull-
SR
/DR = 1, dual-rail opera-
17
FLM
I
18
NC
19
20
21
22
23
GND
R2
V
DDD
T2
ZS
D
O
O
I
coaxial cable operation and set
24
25
26
V
GND
SD
DDA
I
A
LOS
= 0) forces
27
28
R1
T1
I
I
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