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參數(shù)資料
| 型號： | T7288 |
| 廠商： | Lineage Power |
| 英文描述： | CEPT/E1 Line Interface(CEPT/E1 線接口) |
| 中文描述： | CEPT/E1線路接口（CEPT/E1線接口） |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 432K |
| 代理商： | T7288 |
Data Sheet
January 1998
T7288 CEPT/E1 Line Interface
6
Lucent Technologies Inc.
Overview
(continued)
Transmit Converter
The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmis-
sion and sensing of alternately positive and negative pulses. The transmit converter accepts unipolar data and
clock and converts the signal to a balanced bipolar data signal. Binary 1s in the data stream become pulses of
alternating polarity transmitted between the two output rails, T2 and R2. Binary 0s are transmitted as null pulses.
The output pulse waveform is nominally rectangular. The pulses are produced by a high-speed D/A converter and
are driven onto the line by low-impedance output buffers. The positive and negative pulses meet ITU-T specifica-
tion G.703 template requirements. The normalized pulse template is shown in Figure 5. A block diagram of the
analog circuitry is shown in Figure 6.
The clock multiplier shown in Figure 6 uses a phase-locked loop (PLL) to produce the high-speed timing wave-
forms needed to produce a well-controlled pulse width. The clock multiplier also eliminates the need for the tightly
controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are
given in Table 10.
Note: V corresponds to the nominal peak value.
Figure 5. ITU-T G.703 Pulse Template
10%
488 ns
(244 + 244)
219 ns
(244 – 25)
10%
0%
NOMINAL PULSE
269 ns
(244 + 25)
20%
10%
10%
V = 100%
20%
50%
10%
10%
244 ns
194 ns
(244 – 50)
20%
5-3145(C)
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