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參數(shù)資料
| 型號(hào)： | T71L6808A |
| 廠(chǎng)商： | TM Technology, Inc. |
| 英文描述： | Octal 10/100 Switch with Embedded Memory |
| 中文描述： | 八路10/100交換機(jī)嵌入式存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 4/23頁(yè) |
| 文件大小： | 335K |
| 代理商： | T71L6808A |
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tm
Block Diagram
Preliminary T71L6808A
Taiwan Memory Technology, Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date:May. 2001
Revision:0.A
Functional Description
Reset
After power on reset, the T71L6808A will determine some features from ENFCTRL and
ENBKPRS pins, auto-load the content of 24LC02 serial EEPROM, and write abilities to
connected PHY management registers via MDC/MDIO.
RMII Interface
The T71L6808A provides 10/100 Mbps low pin count RMII interface for use between PHY and
T71L6808A. The RMII is capable of supporting 10Mbps and 100Mbps data rates. A single clock
reference, 50MHz, sourced from an external clock input is used for receive and transmit. It also
provides independent 2 bit wide (di-bit) transmit and receive data paths. As the REFCLK is 10
times the data rate in 10Mbps mode each data di-bit must be output on TXD[1:0] and input on
RXD[1:0] for ten consecutive REFCLK cycles.
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