參數(shù)資料
型號： T6829-T3Q
廠商： ATMEL CORP
元件分類： 外設(shè)及接口
英文描述： SIPO BASED PRPHL DRVR, PDSO16
封裝： POWER, SO-16
文件頁數(shù)： 2/16頁
文件大?。?/td> 184K
代理商： T6829-T3Q
10
T6819/T6829 [Preliminary]
4531D–BCD–07/04
4.15
Low-side output switch
off delay
(1),(2)
V
VS =13 V
RLoad = 30
t
doff
3s
A
4.16
Dead time between
corresponding high-
and low-side switches
VVS =13 V
R
Load = 30
t
don - tdoff
1
s
A
4.17
t
dPWM
low-side switch
(3)
V
VS = 13 V
R
Load = 30
t
dPWM =
t
don - tdoff
20
s
A
4.18
t
dPWM
high-side switch
(3)
V
VS = 13 V
R
Load = 30
t
dPWM =
t
don - tdoff
3
7
s
A
5
Logic Inputs DI, CLK, CS, PWM
5.1
Input voltage low-level
threshold
5-8
VIL
0.3
×
V
VCC
V
A
5.2
Input voltage high-level
threshold
5-8
V
IH
0.7
×
V
VCC
V
A
5.3
Hysteresis of input
voltage
5-8
V
I
50
700
mV
A
5.4
Pull-down current
Pins DI, CLK, PWM
VDI, VCLK, VPWM = VCC
6, 7, 8
IPD
10
65
A
5.5
Pull-up current
Pin CS
V
CS = 0 V
5
I
PU
-65
-10
A
6
Serial Interface – Logic Output DO
6.1
Output-voltage low
level
I
DOL = 2 mA
10
V
DOL
0.4
V
A
6.2
Output-voltage high
level
IDOL = -2 mA
10
VDOH
V
VCC-
0.7 V
V
A
6.3
Leakage current
(tri-state)
VCS = VCC
0V < V
DO < VVCC
10
IDO
-10
10
A
7
Inhibit Input – Timing
7.1
Delay time from
standby to normal
operation
tdINH
100
s
A
Electrical Characteristics (Continued)
7.5 V < V
S < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
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