參數(shù)資料
型號： T6829-T3Q
廠商： ATMEL CORP
元件分類： 外設(shè)及接口
英文描述： SIPO BASED PRPHL DRVR, PDSO16
封裝： POWER, SO-16
文件頁數(shù)： 15/16頁
文件大?。?/td> 184K
代理商： T6829-T3Q
8
T6819/T6829 [Preliminary]
4531D–BCD–07/04
Noise and Surge Immunity
Note:
1. Test pulse 5: V
smax = 40 V.
Parameters
Test Conditions
Value
Conducted interferences
ISO 7637-1
Level 4
(1)
Interference suppression
VDE 0879 Part 2
Level 5
ESD (Human Body Model)
ESD S 5.1
2 kV
ESD (Machine Model)
JEDEC A115A
200 V
Electrical Characteristics
7.5 V < V
S < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
1.1
Quiescent current VS
V
VS < 20 V, SI = low
12
I
VS
1
5
A
1.2
Quiescent current VCC
4.75 V < V
VCC < 5.25 V,
SI = low
11
I
VCC
60
100
A
1.3
Supply current VS
V
VS < 20 V normal
operating, all outputs
off, input register bit 13
(OLD) = high
12
I
VS
4
6
mA
A
1.4
Supply current VCC
4.75 V < V
VCC < 5.25 V,
normal operating
11
IVCC
350
650
A
1.5
Discharge current VS
V
VS = 32.5 V, INH = low
12
I
VS
0.5
5.5
mA
A
1.6
Discharge current VS
V
VS = 40 V, INH = low
12
I
VS
2.5
10
mA
A
2
Undervoltage Detection, Power-on Reset
2.1
Power-on reset
threshold
11
V
VCC
3.2
3.9
4.4
V
A
2.2
Power-on reset delay
time
After switching on V
CC
t
dPor
30
95
190
s
A
2.3
Undervoltage-detection
threshold
VCC =5 V
12
VUv
5.6
7.0
V
A
2.4
Undervoltage-detection
hysteresis
V
CC = 5 V
12
V
Uv
0.6
V
A
2.5
Undervoltage-detection
delay time
t
dUV
10
40
s
A
3
Thermal Prewarning and Shutdown
3.1
Thermal prewarning set
T
jPW set
120
145
170
° C
B
3.2
Thermal prewarning
reset
TjPW reset
105
130
155
° C
B
3.3
Thermal prewarning
hysteresis
T
jPW
15
K
B
3.4
Thermal shutdown off
T
j switch off
150
175
200
° C
B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
相關(guān)PDF資料
PDF描述
T6829-T3S SIPO BASED PRPHL DRVR, PDSO16
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