參數(shù)資料
型號： T6829-T3Q
廠商： ATMEL CORP
元件分類： 外設(shè)及接口
英文描述： SIPO BASED PRPHL DRVR, PDSO16
封裝： POWER, SO-16
文件頁數(shù)： 16/16頁
文件大?。?/td> 184K
代理商： T6829-T3Q
9
T6819/T6829 [Preliminary]
4531D–BCD–07/04
3.5
Thermal shutdown on
T
j switch on
135
160
185
° CB
3.6
Thermal shutdown
hysteresis
T
j switch off
15
K
B
3.7
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
T
jPW set
1.05
1.2
B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
T
j switch on/
TjPW reset
1.05
1.2
B
4
Output Specification (OUT1-OUT3)
4.1
On resistance
I
Out 1-3 H = -1.3 A
4, 13,
14
R
DSOn1-3H
1.1
A
4.2
I
Out 1-3 L = 1.3 A
2, 3, 15
R
DSOn1-3L
1.1
A
4.3
High-side output
leakage current
V
Out 1-3 H = 0 V,
output stages off
4, 13,
14
I
Out1-3H
-5
A
4.4
Low-side output
leakage current
V
Out 1-3 L = VVS,
output stages off
2, 3, 15
IOut1-3L
5
A
4.5
High-side switch
reverse diode forward
voltage
I
Out = 1.5 A
4, 13,
14
V
Out1-3 - VVS
1.5
V
A
4.6
Low-side switch
reverse diode forward
voltage
I
Out 1-3 L = -1.5 A
2, 3, 15
V
Out1-3L
-1.5
V
A
4.7
High-side overcurrent
limitation and shutdown
threshold
4, 13,
14
I
Out1-3H
-2.5
-2
-1.5
A
4.8
Low-side overcurrent
limitation and shutdown
threshold
2, 3, 15
IOut1-3L
1.5
2
2.5
A
4.9
Overcurrent shutdown
delay time
t
dSd
10
40
s
A
4.10
High-side open load
detection current
Input register bit 13
(OLD) = low, output off
4, 13,
14
IOut1-3H
-2.5
-0.2
mA
A
4.11
Low-side open load
detection current
Input register bit 13
(OLD) = low, output off
2, 3, 15
I
Out1-3L
0.2
2.5
mA
A
4.12
High-side output switch
on delay
(1),(2)
V
VS = 13 V
R
Load =30
t
don
20
s
A
4.13
Low-side output switch
on delay
(1),(2)
V
VS = 13 V
RLoad =30
tdon
20
s
A
4.14
High-side output switch
off delay
(1),(2)
VVS =13 V
R
Load = 30
t
doff
20
s
A
Electrical Characteristics (Continued)
7.5 V < V
S < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.
3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.
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