參數(shù)資料
型號(hào): T5743P6-TGQ
廠商: ATMEL CORP
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: UHF ASK/FSK Receiver
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SO-20
文件頁(yè)數(shù): 20/41頁(yè)
文件大?。?/td> 681K
代理商: T5743P6-TGQ
20
T5743
4569A–RKE–12/02
Figure 24.
Data Clock Disappears Because of a Logical Error
Figure 25.
Output of the Data Clock After a Successful Bit Check
The delay of the data clock is calculated as follows:
t
Delay
= t
Delay1
+ t
Delay2
t
Delay1
is the delay between the internal signals Data_Out and Data_In. For the rising
edge, t
Delay1
depends on the capacitive load C
L
at Pin DATA and the external pull-up
resistor R
pup
. For the falling edge, t
Delay1
depends additionally on the external voltage V
X
(see Figure 26, Figure 27 and Figure 34). When the level of Data_In is equal to the level
of Data_Out, the data clock is issued after an additional delay t
Delay2
.
Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive
load at Pin DATA is exceeded, the data clock disappears (see section “Data Interface”).
Dem_out
Data_out (DATA)
DATA_CLK
'1'
'1'
'1'
'0'
'1'
'1'
''
'0'
'0'
'1'
'0'
Logical error (Manchester code violation)
Data
Receiving mode,
bit check aktive
Receiving mode,
data clock control
logic active
Dem_out
Data_out (DATA)
DATA_CLK
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Bit check ok
Data
Receiving mode,
bit check active
Receiving mode,
data clock control
logic active
Start bit
相關(guān)PDF資料
PDF描述
T5744 UHF ASK Receiver
T5744-TGQ UHF ASK Receiver
T5744-TGS UHF ASK Receiver
T5744-TKQ UHF ASK Receiver
T5744-TKS UHF ASK Receiver
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