參數(shù)資料
型號: T5743P6-TGQ
廠商: ATMEL CORP
元件分類: 通信及網絡
英文描述: UHF ASK/FSK Receiver
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: SO-20
文件頁數(shù): 15/41頁
文件大小: 681K
代理商: T5743P6-TGQ
15
T5743
4569A–RKE–12/02
Figure 15.
Timing Diagram for Failed Bit Check (Condition: CV_Lim Lim_max)
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T
Bit-check
varies for each check. Therefore, an average value for T
Bit-check
is given in the electrical
characteristics. T
Bit-check
depends on the selected baud-rate range and on T
Clk
. A higher
baud-rate range causes a lower value for T
Bit-check
resulting in a lower current consump-
tion in polling mode.
In the presence of a valid transmitter signal, T
Bit-check
is dependent on the frequency of
that signal, f
Sig
, and the count of the checked bits, N
Bit-check
. A higher value for N
Bit-check
thereby results in a longer period for T
Bit-check
requiring a higher value for the transmitter
pre-burst T
Preburst
.
Receiving Mode
If the bit check was successful for all bits specified by N
Bit-check
, the receiver switches to
receiving mode. According to Figure 11, the internal data signal is switched to Pin DATA
in that case and the data clock is available after the start bit has been detected (Figure
22). A connected microcontroller can be woken up by the negative edge at Pin DATA or
by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is
switched back to polling mode explicitly.
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud-rate range (BR_Range). Figure 16 illustrates how Dem_out is syn-
chronized by the extended clock cycle T
XClk
. This clock is also used for the bit-check
counter. Data can change its state only after T
XClk
has elapsed. The edge-to-edge time
period t
ee
of the Data signal as a result is always an integral multiple of T
XClk
.
The minimum time period between two edges of the data signal is limited to t
ee
T
DATA_min
. This implies an efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.
The maximum time period for DATA to stay Low is limited to T
DATA_L_max
. This function is
employed to ensure a finite response time in programming or switching off the receiver
via Pin DATA. T
DATA_L_max
is thereby longer than the maximum time period indicated by
the transmitter data stream. Figure 18 gives an example where Dem_out remains Low
after the receiver has switched to receiving mode.
Bit check
IC_ACTIVE
Bit-check-
counter
0
2 3 4
5 6
2
4 5
1
7
3
6
7 8 9
11 12
10
1/2 Bit
Start-up mode
20
( Lim_min = 14, Lim_max = 24 )
Sleep mode
Bit check failed ( CV_Lim >= Lim_max )
13 14 15 16 17 18 19
21 22 23 24
0
1
Dem_out
Bit-check mode
T
Start-up
T
Bit-check
T
Sleep
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相關代理商/技術參數(shù)
參數(shù)描述
T5743P6-TGS 功能描述:IC RCVR300-450MHZ ASK/FSK 20SOIC RoHS:否 類別:RF/IF 和 RFID >> RF 接收器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 09/Jan/2012 標準包裝:50 系列:* 頻率:850MHz ~ 2.175GHz 靈敏度:- 數(shù)據傳輸率 - 最大:- 調制或協(xié)議:- 應用:* 電流 - 接收:* 數(shù)據接口:PCB,表面貼裝 存儲容量:- 天線連接器:PCB,表面貼裝 特點:- 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 85°C 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP(6x6) 包裝:托盤
T5744 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:UHF ASK Receiver
T5744N-TGQ 功能描述:IC RCVR PLL ASK 450MHZ 20-SOIC RoHS:否 類別:RF/IF 和 RFID >> RF 接收器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 09/Jan/2012 標準包裝:50 系列:* 頻率:850MHz ~ 2.175GHz 靈敏度:- 數(shù)據傳輸率 - 最大:- 調制或協(xié)議:- 應用:* 電流 - 接收:* 數(shù)據接口:PCB,表面貼裝 存儲容量:- 天線連接器:PCB,表面貼裝 特點:- 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 85°C 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP(6x6) 包裝:托盤
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T5744N-TGSY 制造商:Atmel Corporation 功能描述: