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參數(shù)資料
| 型號(hào)： | SY89537LMY |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER/FANOUT BUFF 44MLF |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | Precision Edge® |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-VFQFN 裸露焊盤，44-MLF? |
| 供應(yīng)商設(shè)備封裝： | 44-MLF?（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-3239 |
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Micrel, Inc.
SY89537L
December 2007
M9999-121207-B
hbwhelp@micrel.com or (408) 955-1690
15
Figure 6 shows the open and closed loop gain of the
SY89537L. The closed loop-gain plot shows that the
SY89537L when configured with the recommended
loop filter values has essentially no jitter peaking near
the -3dB point. In addition, the open loop curve shows
the frequency at which unity gain occurs for a typical
case of the SY89537L with VCC = 3.3V at TA = 25°C.
At unity gain, Figure 7 can be used to determine the
phase margin or stability of the SY89537L.
Figure 6. Open and Closed Loop Gain
at VCC = 3.3V, TA = 25°C
Figure 7. Phase Margin Plot
at VCC = 3.3V, TA = 25°C
Figure 8 illustrates the VCO frequency versus the loop
filter control voltage at 3.3V, TA = 25°C. The normal
loop filter control voltage is -300mV to +300mV.
Figure 9 illustrates the VCO gain curve at VCC = 3.3V,
TA = 25°C. With this set of information, determining
the loop stability with other sets of loop filter
configurations are possible.
Figure 8. VCO Frequency vs.
Loop Filter Control Voltage at 3.3V, TA = 25°C
Figure 9. VCO Gain vs.
Loop Filter Control Voltage at 3.3V, TA = 25°C
Input Interface
RFCK is designed to accept any differential or single-
ended input signal 300mV above VCC or 300mV below
GND. RFCK should not be left floating. Tie either the
true or complement input to GND, but not both. A logic
zero is achieved by connecting the complement input
to GND with the true input floating. For TTL input, tie a
2.5k resistor between the complement input and
GND. LVDS, CML and HSTL differential signals may
be connected directly to the reference inputs.
Figure 10. Simplified Input Structure
dB
Phase
M
argin
(
°)
Frequency (Hz)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89537LMY TR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89538L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer |
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