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參數(shù)資料
| 型號： | SY89537LMY |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER/FANOUT BUFF 44MLF |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | Precision Edge® |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | CMOS，HSTL，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 756MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-VFQFN 裸露焊盤，44-MLF? |
| 供應(yīng)商設(shè)備封裝： | 44-MLF?（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-3239 |
Micrel, Inc.
SY89537L
December 2007
M9999-121207-B
hbwhelp@micrel.com or (408) 955-1690
4
Pin Description
Power
Pin Number
Pin Name
Pin Function
1
VCCA
Analog PLL Power Pin: Connects to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB. Bypass with
0.1F//0.01F low ESR capacitors and place as close to the VCCA pin as possible.
3
VCCD
Digital Logic Core Power Pin: VCCD connects to a 3.3V supply. Power pins are not internally
connected on the die, and must be connected together on the PCB. Bypass with
0.1F//0.01F low ESR capacitors and place bypass capacitors as close to the VCCD pin as
possible.
14, 27, 30, 36
VCCO
LVDS and LVPECL Output Driver Power Pins: The outputs can be powered from a 2.5V
supply or 3.3V supply. Connect all VCCO pins to the same power supply: 3.3V ±10% or 2.5V
±5%. Power pins are not internally connected on the die, and must be connected together on
the PCB. Bypass with 0.1F//0.01F low ESR capacitor and place as close to the VCCO pin
as possible.
10
GNDA
PLL Ground: Connect to “quiet” ground. GNDA and GND are not internally connected on the
die, and must be connected on the PCB.
11, 21, 22
GND,
Exposed Pad
Ground: GND pins and exposed pad must both be connected to the most negative potential
of the chip ground.
Control and Configuration
Pin Number
Pin Name
Pin Function
43
LR
Analog Input/Output: Provides the reference voltage for the PLL loop filter and is used with the
LF pin. See "External Loop Filter Considerations" for recommended loop filter values.
44
LF
Analog Input/Output: Provides the loop filter node for the PLL. See “External Loop Filter
Considerations” for loop filter values.
2, 4
RSEL1, RSEL0
TTL/CMOS Reference Input Pre-scaler. The two-bit input pre-scaler divides the input
reference frequency by /1, /2, /4, or /8. RSEL0 is the LSB bit. See "Reference Input Divider
Select Table," for proper decoding. The threshold voltage VTH = VCC/2. Internal 25k pull-up.
7
INSEL
TTL/CMOS Input Select Control. Selects either XTAL or Reference (RFCK) input. Internal
25k pull-up. The default is logic HIGH, and selects the XTAL input. The threshold voltage VTH
= VCC/2.
Logic HIGH: XTAL Select
Logic LOW: Reference Input Select
23
LSEL
TTL/CMOS input select control signal for the LVDS LOUT0-LOUT2 outputs. LSEL and LEN
are used to decode the selection and the post divider of the LVDS output bank. LSEL includes
an internal 25k pull-up. See “LVDS Output and Frequency Select Table” for proper decoding.
The threshold voltage VTH = VCC/2.
24
LEN
TTL/CMOS Input Enable Pin. Used to control the LOUT0-LOUT2 outputs and acts as a
frequency select pin. LEN and LSEL are used to decode the selection and the post divider of
the LVDS output bank. See the “LVDS Output and Frequency Select Table” for proper
decoding. LEN includes an internal 25k pull-up. When disabled, LOUT0-LOUT2 outputs are
LOW, and the complimentary outputs are HIGH. The threshold voltage VTH = VCC/2.
17
19
39
41
PSEL0
PSEL1
PSEL2
PSEL3
TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PSELx and
PENx are used together to decode the selection and post divider of the PECL outputs. PSELx
pins include an internal 25k pull-up. The threshold voltage VTH = VCC/2. See "PECL Output
Frequency and Select Table" for proper decoding.
18
20
40
42
PEN0
PEN1
PEN2
PEN3
TTL/CMOS input enable pin. Used to control the POUT0-PECL2 outputs and acts as a
frequency select pins. PENx and PSELx are used together; see the “PECL Output and
Frequency Select Table” for proper decoding. PENx includes an internal 25k pull-up. When
disabled, PECL0-PECL2 outputs are LOW. The threshold voltage VTH = VCC/2.
33
SYNC
TTL/CMOS output bank synchronization control. Internal 25k pull-up. The default state is
HIGH. After any bank has been programmed, all PECL and LVDS outputs are synchronized
when the SYNC control pin is toggled with a HIGH-LOW-HIGH transition. See
“Synchronization” section for details. The threshold voltage VTH = VCC/2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY89537LMY TR | 功能描述:時鐘合成器/抖動清除器 3.3V LVPECL/LVDS Clock Synthesizer System (I Temp, Green) RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SY89537LMYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V Precision LVPECL and LVDS |
| SY89538L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_06 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay |
| SY89538L_08 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer |
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