參數(shù)資料
型號: SY89221UMG
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89221 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝: LEAD FREE, TQFP-64
文件頁數(shù): 1/17頁
文件大?。?/td> 828K
代理商: SY89221UMG
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (
408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
September 2006
M9999-092906-A
hbwhelp@micrel.com or (408) 955-1690
SY89221U
Precision 1:15 LVPECL Fanout Buffer with
2:1 MUX and Four ÷1/÷2/÷4 Clock Divider
Output Banks
General Description
The SY89221U is a 2.5/3.3V precision, high-speed,
integrated clock divider and LVPECL fanout buffer
capable of handling clocks up to 1.5GHz. Optimized
for
communications
applications,
the
four
independently controlled output banks are phase-
matched and can be configured for pass through ÷1,
÷2 or ÷4 divider ratios.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows the user to
interface to any differential signal (AC- or DC-coupled)
as small as 100mV (200mVPP) without any level
shifting or termination resistor networks in the signal
path. The low-skew, low-jitter outputs are LVPECL
compatible with extremely fast rise/fall times that are
guaranteed to be less than 220ps.
The /MR (master reset) input asynchronously resets
the outputs. A four-clock delay after de-asserting /MR
allows the counters to synchronize and start the
outputs from the same state without any runt pulse.
The SY89221U is part of Micrel’s Precision Edge
product family. All support documentation can be
found at Micrel's web site at: www.micrel.com.
Features
Four low-skew LVPECL output banks with
independently programmable ÷1, ÷2 and ÷4 divider
options
Four output banks, 15 total outputs
Guaranteed AC performance over temperature and
voltage:
– Accepts a clock frequency up to 1.5GHz
– <1600ps IN-to-OUT propagation delay
– <270ps rise/fall time
– <35 ps within-bank skew
Fail Safe Input
– Prevents outputs from oscillating
Ultra-low jitter design:
– <1psRMS random jitter
– <10psPP total jitter (clock)
Patent-pending input termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
CMOS/TTL-compatible output enable (EN) and
divider select control
2.5V ±5% or 3.3V ±10% power supply
–40°C to +85°C temperature range
Available in 64-pin TQFP
Applications
All SONET/SDH applications
All Fibre Channel applications
All Gigabit Ethernet applications
Markets
LAN/WAN Routers/Switches
Enterprise servers
Storage
ATE
Test and measurement
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