參數(shù)資料
型號: SY89464UMYTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44
封裝: 7 X 7 MM, LEAD FREE, MO-220, MLF-44
文件頁數(shù): 1/19頁
文件大?。?/td> 689K
代理商: SY89464UMYTR
SY89464U
Precision LVPECL 1:10 Fanout with 2:1 Runt
Pulse Eliminator MUX and Internal Termination
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
December 2007
M9999-120607-C
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89464U is a low jitter 1:10 LVPECL fanout
buffer with a 2:1 differential input multiplexer (MUX)
optimized
for
redundant
source
switchover
applications.
Unlike
standard
multiplexers,
the
SY89464U’s unique 2:1 Runt Pulse Eliminator
(RPE) MUX prevents any short cycles or “runt”
pulses during switchover. In addition, a unique Fail-
Safe Input (FSI) protection prevents metastable
output conditions when the selected input clock fails
to a DC voltage (voltage between the pins of the
differential input drops below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal
termination
architecture
that
allows
customers to interface to any differential signal (AC-
or DC-coupled) as small as 100mV (200mVPP)
without any level shifting or termination resistor
networks in the signal path. The outputs are 800mV,
100K-compatible LVPECL with fast rise/fall times
guaranteed to be less than 220ps.
The SY89464U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. The
SY89464U is part of Micrel’s high-speed, Precision
Edge
product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Precision Edge
Features
Selects between two sources, and provides 10
precision LVPECL copies
Guaranteed AC performance over temperature and
supply voltage:
– Wide operating frequency: 1kHz to >1.5GHz
– < 1100ps In-to-Out tpd
– < 220ps tr/tf
Unique, patent-pending MUX input isolation design
minimizes adjacent channel crosstalk
Fail-Safe Input prevents oscillations
Ultra-low jitter design:
– <1psRMS random jitter
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
800mV LVPECL output
2.5V ±5% or 3.3V ±10% supply voltage
Output enable
-40°C to +85°C industrial temperature range
Available in 44-pin (7mm x 7mm) QFN package
Applications
Redundant clock switchover
Fail-safe clock protection
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
相關(guān)PDF資料
PDF描述
SY89464UMY 89464 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44
SY89467UHYTR 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
SY89467UHY 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
SY89482LMG LOW SKEW CLOCK DRIVER, QCC24
SY89482LMGTR LOW SKEW CLOCK DRIVER, QCC24
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