參數(shù)資料
型號: SY89467UHYTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
封裝: LEAD FREE, TQFP-64
文件頁數(shù): 1/15頁
文件大?。?/td> 558K
代理商: SY89467UHYTR
SY89467U
Precision LVPECL 1:20 Fanout with 2:1 MUX
and Internal Termination with Fail-Safe Input
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel +1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
April 2008
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89467U is a 2.5/3.3V, 1:20 LVPECL fanout
buffer with a 2:1 differential input multiplexer (MUX).
A unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (when voltage
between the pins of the differential input drops
significantly below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
outputs are 800mV, LVPECL with fast rise/fall times
guaranteed to be less than 270ps.
The SY89467U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. The
SY89467U is part of Micrel’s high-speed, Precision
Edge
product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Functional Block Diagram
Precision Edge
Features
Selects between two inputs, and provides 20
precision LVPECL copies
Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
Guaranteed AC performance over temperature and
supply voltage:
– DC-to >1.5 GHz throughput
– < 1200ps Propagation Delay (In-to-Q)
– 270ps Rise/Fall times
Ultra-low jitter design:
– <1psRMS random jitter
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Wide input voltage range: V
CC to GND
2.5V ±5% or 3.3V ±10% supply voltage
-40°C to +85°C industrial temperature range
Available in 64-pin TQFP package
Applications
Fail-safe clock protection
SONET clock distribution
Backplane distribution
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
相關(guān)PDF資料
PDF描述
SY89467UHY 89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
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