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參數(shù)資料
| 型號： | SY89200UTR |
| 廠商： | MICREL INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, MLF-32 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 129K |
| 代理商： | SY89200UTR |
5
SY89200U
Micrel
M9999-061704
hbwhelp@micrel.com or (408) 955-1690
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100 across all outputs (Q and /Q), unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
fMAX
Maximum Operating Frequency
VOUT >200mV
Clock
1.5
GHz
tpd
Differential Propagation Delay
IN-to-Q
500
700
900
ps
/MR-to-Q
900
ps
tRR
Reset Recovery Time
/MR(L-H)-to-(L-H)
900
ps
tTempco
Differential Propagation Delay
Temperature Coefficient
115
fs/
°C
tSKEW
Within-Bank Skew
Within same fanout bank, Note 9
10
25
ps
Bank-to-Bank Skew
Same divide setting, Note 10
15
35
ps
Bank-to-Bank Skew
Dfferent divide setting, Note 10
25
50
ps
Part-to-Part Skew
Note 11
200
ps
tJITTER
Random Jitter (RJ)
Note 12
1psrms
Total Jitter (TJ)
Note 13
10
pspp
Cycle-to-Cycle Jitter
Note 14
1psrms
tr, tf
Rise/Fall Time
20% to 80%, at full output swing.
40
80
150
ps
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
8. Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC-parameters are guaranteed by
design and characterization.
9. Within-bank is the difference in propagation delays among the outputs within the same bank.
10. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
between each bank, after MR is applied.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
12. RJ is measured with a K28.7 comma detect character pattern.
13. Total jitter definition: with an ideal clock input of frequency
≤f
MAX, no more than one output edge in 10
12 output edges will deviate by more than the
specified peak-to-peak jitter value.
14. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn – Tn–1 where T is the time between rising edges of the output
signal.
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100 across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output HIGH Voltage; (Q, /Q)
See Figure 5a.
1.475
V
VOL
Output LOW Voltage; (Q, /Q)
See Figure 5a.
0.925
V
VOUT
Output Voltage Swing; (Q, /Q)
See Figure 1a.
250
350
mV
VDIFF-OUT
Differential Output Voltage Swing
See Figure 1b.
500
700
mV
|Q - /Q|
VOCM
Output Common Mode Voltage
See Figure 5b.
1.125
1.275
V
(Q, /Q)
V
OCM
Change in Common Mode Voltage
See Figure 5b.
–50
+50
mV
(Q, /Q)
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS(7)
AC ELECTRICAL CHARACTERISTICS(8)
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