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參數資料
| 型號： | SY89112UMYTR |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 89112 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC44 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220, MLF-44 |
| 文件頁數： | 9/14頁 |
| 文件大小： | 689K |
| 代理商： | SY89112UMYTR |
Micrel, Inc.
SY89112U
March 2011
4
M9999-030211-E
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
2, 5
7, 10
CLK0, /CLK0
CLK1, /CLK1
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept
AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50
Ω. Note that these inputs will default to an indeterminate state if
left open. Please refer to the “Input Interface Applications” section for more details.
3, 8
VT0, VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The
VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input
Interface Applications” section for more details.
4, 9
VREF-AC0
VREF-AC1
Reference Voltage: These outputs bias to VCC–1.2V. They are used when AC coupling the
inputs (CLK, /CLK). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with
a 0.01
μF low ESR capacitor to VCC. See “Input Interface Applications” section for more details.
Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin
is only intended to drive its respective VT pin.
44
CLK_SEL
This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that
this input is internally connected to a 25k
Ω pull-up resistor and will default to a logic HIGH state if
left open.
12
EN
This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The
synchronous enable ensures that enable/disable will only occur when the outputs are in a logic
LOW state. Note that this input is internally connected to a 25k
Ω pull-up resistor and will default
to logic HIGH state (enabled) if left open.
13,22,23,28,
33,34,43
VCC
Positive power supply. Bypass with 0.1
μF//0.01μF low ESR capacitors and place as close to
each VCC pin as possible.
42, 41
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
15, 14
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
Q10, /Q10
Q11, /Q11
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies
of the inputs. Please refer to the truth table below for details. Unused output pairs may be left
open. Terminate with 50 to VCC–2V. See “LVPECL Output Interface Applications” section for
more details.
1, 6, 11
GND,
Exposed Pad
Ground. GND pins and exposed pad must both be connected to the most negative potential of
chip the ground.
Truth Table
EN
CLK_SEL
Q
/Q
H
L
CLK0
/CLK0
H
CLK1
/CLK1
L
X
L
(1)
H
(1)
Notes:
1.
Transition occurs on next negative transition of the non-inverted input.
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