參數(shù)資料
型號(hào): SY100E016
廠商: Micrel Semiconductor,Inc.
元件分類: 通用總線功能
英文描述: 8-Bit Synchronous Binary Up Counter(8位同步二進(jìn)制加法器)
中文描述: 8位二進(jìn)制計(jì)數(shù)器同步最多(8位同步二進(jìn)制加法器)
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 116K
代理商: SY100E016
Pin
Function
P
0
-P
7
Parallel Data (Preset) Inputs
Q
0
-Q
7
Data outputs
CE
Count Enable Control Input
PE
Parallel Load Enable Control Input
MR
Master Reset
CLK
Clock
TC
Terminal Count Output
TCLD
TC-Load Control Input
V
CCO
V
CC
to Output
I
700MHz min. count frequency
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
1000ps CLK to Q, TC
I
Internal, gated TC feedback
I
8 bits wide
I
Fully synchronous counting and TC generation
I
Asynchronous Master Reset
I
Fully compatible with industry standard 10KH,
100K I/O levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E016
I
Available in 28-pin PLCC package
The SY10/100E016 are high-speed synchronous,
presettable and cascadable 8-bit binary counters designed
for use in new, high-performance ECL systems. Architecture
and operation are the same as the Motorola MC10H016 in
the MECL 10KH family, extended to 8 bits, as shown in the
logic diagram.
The counters feature internal feedback of TC, gated by
the TCLD (terminal count load) pin. When TCLD is LOW,
the TC feedback is disabled and counting proceeds
continuously, with TC going LOW to indicate an all-HlGH
state. When TCLD is HIGH, the TC feedback causes the
counter to automatically reload upon TC = LOW, thus
functioning as a programmable counter.
8-BIT SYNCHRONOUS
BINARY UP COUNTER
SY10E016
SY100E016
FEATURES
DESCRIPTION
PIN CONFIGURATION
PIN NAMES
Rev.: D
Issue Date:
Amendment: /2
May, 1998
V
EE
NC
MR
CLK
TCLD
P
0
P
1
V
C
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
5
6
7
8
9
10 11
Q
2
Q
1
Q
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
P
5
PLCC
TOP VIEW
J28-1
T
C
P
P
6
P
7
Q
0
V
C
P
4
P
3
P
2
1
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