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參數(shù)資料
| 型號： | SY100E111 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | 1:9 Differential Clock Driver with Enable(帶使能端9選1差分時鐘驅動器) |
| 中文描述： | 1:9差分時鐘驅動器，帶有啟用（帶使能端9選1差分時鐘驅動器） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 78K |
| 代理商： | SY100E111 |
BLOCK DIAGRAM
IN
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
IN
EN
FEATURES
I
Low skew
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
Guaranteed skew limits
I
Differential design
I
V
BB
output
I
Enable input
I
Fully compatible with industry standard 10KH, 100K
I/O levels
I
75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E111
I
Available in 28-pin PLCC package
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01
μ
F
capacitor.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
DESCRIPTION
Rev.: B
Issue Date: February, 1998
Amendment: /2
ClockWorks
SY10E111
SY100E111
1
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PDF描述 |
|---|---|
| SY100E112JY | QUAD DRIVER |
| SY100E112JYTR | QUAD DRIVER |
| SY100E141JY | 8-BIT SHIFT REGISTER |
| SY100E141JYTR | 8-BIT SHIFT REGISTER |
| SY100E151JI | 6-BIT D REGISTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E111A/L | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE) |
| SY100E111AE | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE) |
| SY100E111AEJC | 功能描述:IC CLK FANOUT BUFFER 1:9 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100E, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100E111AEJC TR | 功能描述:IC CLK FANOUT BUFFER 1:9 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅動器 系列:100E, Precision Edge® 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| SY100E111AEJCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/ENABLE) |
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