參數(shù)資料
型號(hào): SY100E141JYTR
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 8-BIT SHIFT REGISTER
中文描述: 100E SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁(yè)數(shù): 1/4頁(yè)
文件大小: 71K
代理商: SY100E141JYTR
1
SY10E141
SY10E141
SY100E141
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
I
700MHz min. shift frequency
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
8 bits wide
I
Bi-directional
I
Four selectable modes for full functionality
I
Asynchronous Master Reset
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E141
I
Pin-compatible with E241
I
Available in 28-pin PLCC package
FEATURES
The SY10/100E141 are 8-bit, full-function shift registers
designed for use in new, high-performance ECL systems.
The E141 performs serial/parallel in and serial/parallel out,
shifting in either direction. The eight inputs D
0
–D
7
accept
parallel input data, while DL/DR accept serial input data for
left/right shifting.
The two select pins, SEL
0
and SEL
1
permit four modes
of operation: Load, Hold, Shift Left and Shift Right, as
shown in the Truth Table. Input data is clocked into the
register on the rising clock edge after meeting the minimum
set-up time. A logic HIGH on the Master Reset (MR) pin
asynchronously resets all the registers to zero.
DESCRIPTION
BLOCK DIAGRAM
D
Q
R
D
Q
D
Q
R
D
7
Q
7
D
Q
R
D
0
Q
0
DL
DR
BITS 1-6
SEL1
SEL0
CLK
MR
8-BIT SHIFT
REGISTER
Rev.: E
Issue Date:
Amendment: /0
March 2006
Pin
Function
D
0
-D
7
Parallel Data Inputs
DL, DR
Serial Data Inputs
SEL
0
, SEL
1
Mode Select Inputs
CLK
Clock
Q
0
-Q
7
Data Outputs
MR
Master Reset
V
CCO
V
CC
to Output
PIN NAMES
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