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參數(shù)資料
| 型號： | SX28 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| 中文描述： | 配置通信控制器與電子工程/閃存程序存儲器，在系統(tǒng)編程能力和片上調(diào)試 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 688K |
| 代理商： | SX28 |
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2000 Scenix Semiconductor, Inc. All rights reserved.
- 28 -
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
Figure 12-3 shows the on-chip Power-On Reset
sequence where the MCLR and V
dd
pins are tied
together. The V
dd
signal is stable before the DRT time-
out period expires. In this case, the device will receive a
proper reset. However, Figure 12-4 depicts a situation
where V
dd
rises too slowly. In this scenario, the DRT will
time-out prior to V
dd
reaching a valid operating voltage
level (V
dd
min). This means the device will come out of
reset and start operating with the supply voltage not at a
valid level. In this situation, it is recommended that you
use the external RC circuit shown in Figure 12-5. The RC
delay should exceed the time period it takes V
dd
to reach
a valid operating voltage
Note 1: The external Power-On Reset circuit is required
only if V
dd
power-up is too slow. The diode D helps dis-
charge the capacitor quickly when V
dd
powers down.
Note 2: R < 40 k
is recommended to make sure that
voltage drop across R does not violate the device electri-
cal specifications.
Note 3: R1 = 100
to 1k
will limit any current flowing
into MCLR from external capacitor C. This helps prevent
MCLR pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
13.0
The on-chip brown-out detection circuitry resets the
device when V
dd
dips below the specified brown-out volt-
age. The device is held in reset as long as V
dd
stays
below the brown-out voltage. The device will come out of
reset when V
dd
rises above the brown-out voltage. The
brown-out level is preset to approximately 4.2V at the
factory. The brown-out circuit can be disabled through
BOR0 and BOR1 bits contained in the FUSEX Word reg-
ister.
BROWN-OUT DETECTOR
Figure 12-3. Time-out Sequence on Power-up
(MCLR tied to V
dd
): Fast V
dd
Rise Time
Figure 12-4. Time-out Sequence on Power-up
(MCLR tied to V
dd
): Slow Rise Time
V
dd
MCLR
POR
drt_time_out
RESET
Tdrt
V
dd
MCLR
POR
drt_time_out
RESET
Tdrt
V1
Figure 12-5. External Power-On Reset Circuit
(For Slow V
dd
Power-up)
V
dd
R
C
MCLR
D
R1
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