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參數(shù)資料
| 型號： | SX28 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| 中文描述： | 配置通信控制器與電子工程/閃存程序存儲器，在系統(tǒng)編程能力和片上調(diào)試 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 688K |
| 代理商： | SX28 |
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2000 Scenix Semiconductor, Inc. All rights reserved.
- 27 -
www.scenix.com
SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75
12.0
Power-On-Reset, Brown-Out reset, watchdog reset, or
external reset initializes the device. Each one of these
reset conditions causes the program counter to branch to
the top of the program memory. For example, on the
device with 2048K words of program memory, the pro-
gram counter is initialized to 07FF.
The device incorporates an on-chip Power-On Reset
(POR) circuit that generates an internal reset as V
dd
rises
during power-up. Figure 12-1 is a block diagram of the
circuit. The circuit contains an 10-bit Delay Reset Timer
(DRT) and a reset latch. The DRT controls the reset time-
out delay. The reset latch controls the internal reset sig-
nal. Upon power-up, the reset latch is set (device held in
reset), and the DRT starts counting once it detects a valid
logic high signal at the MCLR pin. Once DRT reaches the
end of the timeout period (typically 72 msec), the reset
latch is cleared, releasing the device from reset state.
RESET
Figure 12-2 shows a power-up sequence where MCLR is
not tied to the V
dd
pin and V
dd
signal is allowed to rise
and stabilize before MCLR pin is brought high. The
device will actually come out of reset T
drt
msec after
MCLR goes high.
The brown-out circuitry resets the chip when device
power (V
dd
) dips below its minimum allowed value, but
not to zero, and then recovers to the normal value.
.
Note:Ripple counter is 10 bits for Power on Reset (POR)
only.
Figure 12-1. Block Diagram of On-Chip Reset Circuit
POR
BROWN-OUT
MIWU
MCLR/Vpp pin
wdt_time_out
10-Bit Asynch
Ripple
Counter
(DRT Start-Up
Timer)
V
dd
rc_clk
drt_time
_out
S
R
Q
QN
RESET
POR
enable
Figure 12-2. Time-Out Sequence on Power-Up
(MCLR not tied to V
dd
)
V
dd
MCLR
POR
drt_time_out
RESET
Tdrt
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|---|---|
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| SX28AA100-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AA100-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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