參數(shù)資料
型號: STV9937P
廠商: 意法半導體
英文描述: 120-MHz On-Screen Display for Monitors including PictureBooSTTM and 4 True Independent Window Displays
中文描述: 120 - MHz的屏幕的顯示器,其中包括PictureBooSTTM和4個真正的獨立的窗口顯示顯示
文件頁數(shù): 29/49頁
文件大?。?/td> 441K
代理商: STV9937P
29/49
STV9937
Pixel Clock Generator
6
Pixel Clock Generator
The Pixel Clock Generator is used to synchronize the display clock with the horizontal
synchronisation (Hsync) signal. This generator is based on a PLL function used to perform correct
jitter. The pixel frequency is defined with the horizontal line frequency and the horizontal resolution.
Pixel Frequency (F
PIXEL2
) = 12 x HR[6:0] x f
HLINE
The VCO[1:0] value is used to select the appropriate curve partition of the VCO.
The PLL generates:
a pixel clock for the OSD from 7.68 MHz to 120 MHz: F
PIXEL2
a pixel clock for the PictureBooST
TM
(PB) from 30 to 60 MHz: F
PIXEL1
.
The PictureBooST
TM
pixel clock provides the resolution of the PB pixel.It is locked on the HSYNC
signal and the referenced edge is programmed using the HSP bit.
When the monitor resolution is changing, the micro controller changes the OSD horizontal
resolution to adapt the width of the OSD window. In this case, the frequency of the PB clock is
changing also. So the width and the position and the resolution of the PB window is changing.
Table 33: VCO Curve Partition
VCO Value (Binary)
VCO Curve Partition
00
7.68 MHz < F
PIXEL2
< 15 MHz (Default Value)
01
15
MHz < F
PIXEL2
< 30 MHz
10
30
MHz < F
PIXEL2
< 60 MHz
11
60
MHz < F
PIXEL2
< 120 MHz
Table 34: VCO Range
FWR
FAC
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
00h
0h
VCO[1:0]
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