
Pin description
STR91xF
36/72
4.1
Default pin functions
During and just after reset, all pins on ports 0-9 default to high-impedance input mode until
CPU firmware assigns other functions to the pins. This initial input mode routes all pins on ports
0-9 to be read as GPIO inputs as shown in the “Default Pin Function” column of Table 2.
Simultaneously, certain port pin signals are also routed to other functional inputs as shown in
the “Default Input Function” column of Table 2, and these pin input functions will remain until
CPU firmware makes other assignments. At any time, even after the CPU assigns pins to
alternate functions, the CPU may always read the state of any pin on ports 0-9 as a GPIO input.
CPU firmware may assign alternate functions to port pins as shown in columns “Alternate Input
1” or “Alternate Output 1, 2, 3” of Table 2 by writing to control registers at run-time.
Notes for Table 2:
Notes: 1 STMicroelectronics advises to ground all unused pins on port 0 - 9 to reduce noise
susceptibility, noise generation, and minimize power consumption. There are no internal or
programmable pull-up resistors on ports 0-9.
2 All pins on ports 0 - 9 are 5V tolerant
3 Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive and
8 mA sink.
4 For 8-bit non-muxed EMI operation: Port 8 is eight bits of data, ports 7 and 9 are 16 bits of
address.
5 For 16-bit muxed EMI operation: Ports 8 and 9 are 16 bits of muxed address and data bits, port
7 is up to eight additional bits of high-order address
6 Signal polarity is programmable for interrupt request inputs, EMI_ALE, timer input capture
inputs and output compare/PWM outputs, motor control tach and emergency stop inputs, and
motor control phase outputs.
7 HiZ = High Impedance, V = Voltage Source, G = Ground, I/O = Input/Output
8 STR910F devices do not support USB. On these devices USBDP and USBDN signals are "Not
Used" (USBDN is not connected, USBDP must be pulled up by a 1.5K ohm resistor to VDDQ),
and all functions named “USB" are not available.
9 STR910F 128-pin devices do not support Ethernet. On these devices PHYCLK and all
functions named “MII*" are not available.
Table 2.
Device pin description
Pkg
Pin Name
Signal
T
y
pe
Default Pin
Function
Default Input
Function
Alternate functions
80
pin
128
pin
Alternate
Input 1
Alternate
Output 1
Alternate
Output 2
Alternate
Output 3
-
67
P0.0
I/O
GPIO_0.0,
GP Input, HiZ
MII_TX_CLK,
PHY Xmit clock
I2C0_CLKIN,
I2C clock in
GPIO_0.0,
GP Output
I2C0_CLKOUT,
I2C clock out
ETM_PCK0,
ETM Packet
-
69
P0.1
I/O
GPIO_0.1,
GP Input, HiZ
-
I2C0_DIN,
I2C data in
GPIO_0.1,
GP Output
I2C0_DOUT,
I2C data out
ETM_PCK1,
ETM Packet
-
71
P0.2
I/O
GPIO_0.2,
GP Input, HiZ
MII_RXD0,
PHY Rx data0
I2C1_CLKIN,
I2C clock in
GPIO_0.2,
GP Output
I2C1_CLKOUT,
I2C clock out
ETM_PCK2,
ETM Packet
-
76
P0.3
I/O
GPIO_0.3,
GP Input, HiZ
MII_RXD1,
PHY Rx data
I2C1_DIN,
I2C data in
GPIO_0.3,
GP Output
I2C1_DOUT,
I2C data out
ETM_PCK3,
ETM Packet
-
78
P0.4
I/O
GPIO_0.4,
GP Input, HiZ
MII_RXD2,
PHY Rx data
TIM0_ICAP1,
Input Capture
GPIO_0.4,
GP Output
EMI_CS0n,
EMI Chip Select
ETM_PSTAT0,
ETM pipe status