參數(shù)資料
型號(hào): STPCI2HDYI
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁(yè)數(shù): 90/109頁(yè)
文件大?。?/td> 2430K
代理商: STPCI2HDYI
STPC ATLAS
Issue 1.1 - March 23, 2004
81/109
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 8K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PERR#, PCI_REQ#[2:0].
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor. Figure 6-8
shows a typical implementation.
For more information on layout constraints, go to
the place and route recommendations section.
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-9. This approach is also recommended
when
implementing
the
delay
on
PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
Figure 6-8. Typical PCI clock routing
PCICLKI
PCICLKO
PCICLKA
PCICLKB
PCICLKC
0 - 22
10 - 33
Device A
Device B
Device C
0 - 33pF
Figure 6-9. PCI clock routing with zero-delay clock buffer
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
CY2305
Implementation 1
Implementation 2
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