參數(shù)資料
型號: STPCI2HDYI
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁數(shù): 100/109頁
文件大?。?/td> 2430K
代理商: STPCI2HDYI
STPC ATLAS
90/109
Issue 1.1 - March 23, 2004
6.3.13. JTAG INTERFACE
The STPC integrates a JTAG interface for scan-
chain and on-board testing. The only external
device needed are the pull up resistors. Figure 6-
19 describes a typical implementation using these
devices.
6.4. PLACE AND ROUTE
RECOMMENDATIONS
6.4.1. GENERAL RECOMMENDATIONS
Some STPC Interfaces run at high speed and
need to be carefully routed or even shielded like:
1) Memory Interface
2) PCI bus
3) Graphics and video interfaces
4) 14 MHz oscillator stage
All clock signals have to be routed first and
shielded for speeds of 27MHz or higher. The high
speed signals follow the same constraints, as for
the memory and PCI control signals.
The next interfaces to be routed are Memory, PCI,
and Video/graphics.
All the analog noise-sensitive signals have to be
routed in a separate area and hence can be
routed indepedently.
6.4.2. PLL DEFINITION AND IMPLIMENTATION
PLLs are analog cells which supply the internal
STPC Clocks. To get the cleanest clock, the jitter
on the power supply must be reduced as much as
possible. This will result in a more stable system.
Each of the integrated PLL has a dedicated power
pin so a single power plane for all of these PLLs,
or one wire for each, or any solution in between
which help the layout of the board can be used.
Figure 6-19. Typical JTAG implementation
STPC
TCLK
TDO
3V3
Connector
9
10
1
2
6
7
3
4
8
5
TMS
TDI
TRST
3V3
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