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參數(shù)資料
| 型號： | STPCELITE |
| 廠商： | 意法半導體 |
| 英文描述： | X86 Core General Purpose PC Compatible System - on - Chip |
| 中文描述： | x86內(nèi)核兼容的通用計算機系統(tǒng)-關(guān)于-芯片 |
| 文件頁數(shù)： | 76/87頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | STPCELITE |
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DESIGN GUIDELINES
76/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
6.4.3.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
Figure
6-22
. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
The
Figure 6-23
describes a typical clock delay
implementation. The exact timing constraints are
listed in the PCI section of the
Electrical
Specifications
Chapter.
Figure 6-22. Typical PCI clock routing
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
Note: The value of 22 Ohms corresponds to tracks with Z
0
= 70 Ohms.
PCICLKI
PCICLKO
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C
Figure 6-23. Clocks relationships
PCICLKO
PCICLKI
HCLK
PCICLKx
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STPCE1EDBI | X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1EEBC | X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1EEBI | X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1HEBC | X86 Core General Purpose PC Compatible System - on - Chip |
| STPCE1HEBI | X86 Core General Purpose PC Compatible System - on - Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPCH0.5MBBL | 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U |
| STPCH0.5MBBU | 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U |
| STPCH0.5MBGR | 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U |
| STPCH0.5MBRD | 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U |
| STPCH0.5MBYL | 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U |
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