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| 型號(hào)： | STPCELITE |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | X86 Core General Purpose PC Compatible System - on - Chip |
| 中文描述： | x86內(nèi)核兼容的通用計(jì)算機(jī)系統(tǒng)-關(guān)于-芯片 |
| 文件頁(yè)數(shù)： | 65/87頁(yè) |
| 文件大小： | 1356K |
| 代理商： | STPCELITE |
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DESIGN GUIDELINES
Release 1.3 - January 29, 2002
65/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 2K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PCI_REQ#[2:0].
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor.
Figure 6-7
shows a typical implementation.
For more information on layout constraints, go to
the
place and route recommendations
section.
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-8
. This approach is also recommended
Figure 6-8. PCI clock routing with zero-delay clock buffer
when implementing the delay on PCICLKI
according to the PCI section of the
Electrical
Specifications
chapter.
Figure 6-7. Typical PCI clock routing
PCICLKI
PCICLKO
PCICLKA
PCICLKB
PCICLKC
0 - 22
10 - 33
Device A
Device B
Device C
0 - 33pF
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
PCICLKI
PCICLKO
Device A
Device B
Device C
PLL
Device D
CY2305
CY2305
Implementation 1
Implementation 2
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