參數(shù)資料
型號： STPCE1HEBC
廠商： 意法半導體
英文描述： X86 Core General Purpose PC Compatible System - on - Chip
中文描述： x86內(nèi)核兼容的通用計算機系統(tǒng)-關于-芯片
文件頁數(shù)： 74/87頁
文件大?。?/td> 1356K
代理商： STPCE1HEBC
DESIGN GUIDELINES
74/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
When using DIMM modules, schematics have to
be done carefully in order to avoid data buses
completely crossing on the board. This has to be
checked at the library level. In order to achieve the
layout shown in
Figure 6-19
, schematics have to
implement the crossing described in
Figure 6-20
.
The DQM signals must be exchanged using the
same order.
6.4.2.4. Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50
for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial
for the other signals but if their timing is not as
critical as the address/control signals they could
use the default value. Using a lower impedance
implies using wider traces which may have an
impact on the routing of the board.
The layout of this interface can be validated by an
electrical simulation using the IBIS model
available on the STPC web site.
Figure 6-19. Optimum Data Bus Layout for DIMM
Figure 6-20. Schematics for Optimum Data Bus Layout for DIMM
DIMM
STPC
SDRAM I/F
D[15:00]
D[47:32]
D[31:16]
D[63:48]
MD[31:00]
MD[63:32]
MD[15:00],DQM[1:0]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
DIMM
STPC
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相關代理商/技術參數(shù)
參數(shù)描述
STPCE1HEBI 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCELITE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
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STPCH0.5MBGR 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
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