參數資料
型號： STPCE1HEBC
廠商： 意法半導體
英文描述： X86 Core General Purpose PC Compatible System - on - Chip
中文描述： x86內核兼容的通用計算機系統(tǒng)-關于-芯片
文件頁數： 72/87頁
文件大?。?/td> 1356K
代理商： STPCE1HEBC
DESIGN GUIDELINES
72/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
6.4.2. MEMORY INTERFACE
6.4.2.1. Introduction
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 100 MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For
applications where the memories are directly
soldered to the motherboard, the PCB should be
laid out such that the trace lengths fit within the
constraints shown here. The traces could be
slightly shorter since the extra routing on the
DIMM PCB is no longer present but it is then up to
the user to verify the timings.
6.4.2.2. SDRAM Clocking Scheme
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is
generated on-chip through a PLL and goes
directly to the MCLKO output pin of the STPC. The
nominal frequency is 100 MHz. Because of the
high load presented to the MCLK on the board by
the DIMMs it is recommended to rebuffer the
MCLKO signal on the board and balance the skew
to the clock ports of the different DIMMs and the
MCLKI input pin of STPC.
6.4.2.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in
Figure
6-17
. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to
reduce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100 mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible,
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all components it is
recommended that all the DIMM clock pins, STPC
Figure 6-16. Clock Scheme
D
MCLKI
MCLKO
D
PLL
r
PLL
MA[ ] + Control
MD[63:0]
SDRAM
CONTROLLER
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相關代理商/技術參數
參數描述
STPCE1HEBI 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCELITE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
STPCH0.5MBBL 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
STPCH0.5MBBU 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
STPCH0.5MBGR 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
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