參數(shù)資料
型號： STPCE1HEBC
廠商： 意法半導(dǎo)體
英文描述： X86 Core General Purpose PC Compatible System - on - Chip
中文描述： x86內(nèi)核兼容的通用計算機系統(tǒng)-關(guān)于-芯片
文件頁數(shù)： 6/87頁
文件大?。?/td> 1356K
代理商： STPCE1HEBC
GENERAL DESCRIPTION
6/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power-on state.
- Power control outputs to disable power from
different planes of the board.
Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate an SMI interrupt
to allow the software to bring the system back up
to full power-on state. The chip-set supports up to
three power down states described above; these
correspond to decreasing levels of power savings.
Power down puts the STPC Elite into suspend
mode. The processor completes execution of the
current
instruction,
any
instructions and associated bus cycles. During the
suspend mode, internal clocks are stopped.
Removing power-down, the processor resumes
instruction fetching and begins execution in the
instruction stream at the point it had stopped.
Because of the static nature of the core, no
internal data is lost.
pending
decoded
1.3. JTAG
JTAG stands for Joint Test Action Group and is the
popular name for IEEE Std. 1149.1, Standard Test
Access Port and Boundary-Scan Architec-ture.
This built-in circuitry is used to assist in the test,
maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan register so that a
component is able to respond to a minimum set of
test instructions.
相關(guān)PDF資料
PDF描述
STPCE1HEBI X86 Core General Purpose PC Compatible System - on - Chip
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STPCE1HDBI X86 Core General Purpose PC Compatible System - on - Chip
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STPCE1HEBI 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCELITE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
STPCH0.5MBBL 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
STPCH0.5MBBU 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
STPCH0.5MBGR 制造商:Panduit Corp 功能描述:TX5E SHIELDED PATCH CORD 制造商:Panduit Corp 功能描述:COPPER PATCH CORD, CAT 5E, INTL GRAY F/U
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