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| 型號： | STPCE1DDBC |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 38/87頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | STPCE1DDBC |
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ELECTRICAL SPECIFICATIONS
38/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
4.5.1. POWER ON SEQUENCE
Figure 4-3
describes the power-on sequence of
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications, a margin of 10
μ
s is even
recommended to let the STPC PLLs and strap
options stabilize.
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
Figure 4-3. Power-on timing diagram
Strap Options
Power Supplies
SYSRSTI#
SYSRSTO#
14 MHz
1.6 V
VALID CONFIGURATION
> 10 us
HCLK
PCI_CLK
2.3 ms
ISACLK
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| STPCE1EEBI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip |
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