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參數(shù)資料
| 型號： | STLR4200S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB/lrDA Bridge Controller |
| 中文描述： | 的USB / lrDA橋控制器 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 308K |
| 代理商： | STLR4200S |
18
3-4200-D1-2.0-0403
STIr4200
USB/IrDA Bridge Controller
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
6.1.6.
FIFO Count Registers (LSB,MSB)
Offset 6&7
6.1.6.1.
FIFO Count LSB
Offset 6
6.1.6.2.
FIFO Count MSB
Offset 7
6.1.7.
DPLL Tune Register
Offset 8
7
7
6
5
4
3
2
1
0
FIFO Count Register (LSB)
Default State
FFCNT(7: 0)
0
0
0
0
0
0
0
0
Bit Number Bit Mnemonic Access
Function
7-0
FFCNT(7:0)
RO
When combined with the FIFO Count Registers (MSB), indicates the number
of bytes in the FIFO.
Table 18. FIFO Count LSB
7
6
5
4
3
2
1
0
FIFO Count Register (MSB)
Default State
Reserved
0
FFCNT(12: 8)
0
0
0
0
0
0
0
Bit Number Bit Mnemonic Access
Function
7-5
4-0
Reserved
FFCNT(12:8)
RO
RO
Write as zeros.
When combined with the FIFO Count Registers (LSB), indicates the number
of bytes in the FIFO.
Table 19. FIFO Count MSB
6
5
4
3
2
1
0
DPLL Tune Register
Default State
DPCNT(5: 0)
0
LONGP(1: 0)
1
0
1
1
0
0
0
Bit Number Bit Mnemonic Access
Function
7-2
DPCNT(5: 0)
R/W
Sets the sensitivity of the receiver
’
s digital PLL. This bit should be used for
chip debug purposes only. This register setting only affects FIR mode. The
default setting is proper for normal operation.
Sets the sensitivity of the pulse detector of the receiver. These bits should be
used for chip debug purposes only.
1-0
LONGP(1: 0)
R/W
Table 20. DPLL Tune Register
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