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參數(shù)資料
| 型號： | STLR4200S |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB/lrDA Bridge Controller |
| 中文描述： | 的USB / lrDA橋控制器 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 308K |
| 代理商： | STLR4200S |
14
3-4200-D1-2.0-0403
STIr4200
USB/IrDA Bridge Controller
O F F I C I A L P R O D U C T D O C U M E N T A T I O N
6. DIGITAL IR TRANSCEIVER REGISTERS
6.1.
Detailed STIr4200 Register Descriptions
6.1.1.
FIFO Data Register
Offset 0
Offset
Description
Access
Bit Position
4
Reserved
ASK
PDCLK(7: 0)
TXPWD
BSTUFF
R/W
FFDIR
RO
FFCNT(7:0)
7
6
5
3
2
1
0
0
1
2
3
4
FIFO Data
Mode Register
Baud Rate Register
Control Register
Sensitivity Register
R/W
R/W
R/W
R/W
FIR
Reserved
SIR
FASTRXEN FFRSTEN FFSPRST PDCLK(8)
SDMODE RXSLOW
RXDSNS(2: 0)
DLOOP1
RXPWD
SPWIDTH
R/W
FFCLR
WO
TXPWR(1: 0)
ID(2)
RO
FFEMPTY
RO
SRESET
ID(0)
RO
FFTXERR
ROC
ID(1)
RO
5
Status Register
EOFRAME
RO
FFUNDER
ROC
FFOVER
ROC
FFRXERR
ROC
6
FIFO Count (Note 1)
Register (LSB)
FIFO Count (Note 1)
Register (MSB)
DPLL Tune Register
IRDIG Setup Register
Reserved
Reserved
Reserved
Reserved
Reserved
Test Register
R/W : Read/Write
RO : Read only
ROC : Read only, clear on read
WO : Write only
Note:
1.
Due to double buffering, FFCNT could be off by as much as 3 bytes
RO
7
RO
0
0
0
FFCNT(12: 8)
8
9
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DPCNT(5: 0)
Reserved Reserved Reserved
LONGP(1: 0)
RXHIGH
TXLOW
Reserved Reserved Reserved
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
Reserved
PLLDWN
LOOPIR LOOPUSB TSTENA
TSTOSC(3: 0)
Table 10. Ir Transceiver Registers
7
6
5
4
3
2
1
0
FIFO Data
Default State
Reserved
0
0
0
0
0
0
0
0
Bit Number
Bit Mnemonic
Access
Function
7
–
0
Reserved
R/W
The FIFO data register is used internally by the USB interface to
access the FIFO data in the digital infrared block. Although this
register is accessible through the USB interface, it should never be
accessed during normal operation.
Table 11. FIFO Data Register
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