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參數(shù)資料
| 型號： | STLC2415 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | BLUETOOTH BASEBAND WITH INTEGRATED FLASH |
| 中文描述： | 藍(lán)牙基帶內(nèi)置閃光燈， |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 181K |
| 代理商： | STLC2415 |
17/22
STLC2415
including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), μ-Law (8bit) or
A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is
programmable to be CVSD, A-Law or μ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK : PCM clock
– PCM_SYNC : PCM 8kHz sync
– PCM_A : PCM data
– PCM_B : PCM data
Directions of PCM_A and PCM_B are software configurable.
Figure 6. PCM (A-law,
μ
-law) Standard Mode
Figure 7. Linear Mode
Table 11. PCM Interface Timing.
Symbol
PCM Interface
F
pcm_clk
F
pcm_sync
t
WCH
t
WCL
t
WSH
t
SSC
t
SDC
t
HCD
t
DCD
Description
Min
Typ
Max
Unit
Frequency of PCM_CLK (master)
-
2048
kHz
Frequency of PCM_SYNC
High period of PCM_CLK
8
kHz
ns
200
Low period of PCM_CLK
200
ns
High period of PCM_SYNC
Setup time, PCM_SYNC high to PCM_CLK low
200
100
ns
ns
Setup time, PCM_A/B input valid to PCM_CLK low
100
ns
Hold time, PCM_CLK low to PCM_A/B input invalid
Delay time, PCM_CLK high to PCM_A/B output valid
100
ns
ns
150
D02TL558
PCM_CLK
PCM_SYNC
PCM_A
B
B
PCM_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
125
μ
s
B
D02TL559
PCM_CLK
PCM_SYNC
PCM_A
PCM_B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
125
μ
s
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