參數(shù)資料
型號(hào)： STLC2415
廠商： 意法半導(dǎo)體
英文描述： BLUETOOTH BASEBAND WITH INTEGRATED FLASH
中文描述： 藍(lán)牙基帶內(nèi)置閃光燈，
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 181K
代理商： STLC2415
STLC2415
14/22
6
GENERAL SPECIFICATION
6.1 System Clock
The STLC2415 works with a single clock provided on the XIN pin. The value of this external clock should
be 13MHz ±20ppm (overall).
6.1.1 Slow Clock
The slow clock is used by the baseband as reference clock during the low power modes. Compared to the
13MHz clock, the slow clock only requires an accuracy of ±250ppm (overall).
Several options are foreseen in order to adjust the STLC2415 behaviour according to the features of the
radio used:
– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow
clock is provided by the system, a 32 kHz crystal must be used by the STLC2415 (default mode).
– if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system
provides a slow clock at 32kHz or 3.2kHz, this signal is simply connected to the STLC2415 (lpo_clk_p).
– if the system clock (e.g. 13MHz) is provided at all times, the STLC2415 generates from the 13MHz ref-
erence clock an internal 32kHz clock. This mode is not an optimized mode for power consumption.
6.2 Boot Procedure
The boot code instructions are the first that ARM7TDMI executes after an HW reset. All the internal de-
vice's registers are set to their default value.
There are 2 types of boot:
– Flash boot.
When boot pin is set to `1` (connected to VDD), the STLC2415 boots on its flash memory.
– UART download boot from ROM.
When boot pin is set to `0` (connected to GND), the STLC2415 boots on its internal ROM (needed to
download the new firmware in the flash). When booting on the internal ROM, the STLC2415 will monitor
the UART interface for approximately 1.4 second. If there is no request for code downloading during this
period, the ROM jumps to flash.
6.3 Clock Detection
The STLC2415 has an automatic slow clock frequency detection (32kHz, 3.2kHz or none).
6.4 Master Reset
When the device's reset is held active (NRESET is low), UART1_TXD and UART2_TXD are set to input
state. When the NRESET returns high, the device starts to boot.
Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete
reset of the device.
6.5 Interrupts/Wake-up
The external pins int1 and int2, and up to 8 GPIOs can be used both as external interrupt source and as
wake-up source. In addition the chip can be woken-up by USB, UART1_RXD, UART2_RXD.
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