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參數(shù)資料
| 型號： | STK6005 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | converting PC / Mac video images for a TFT-LCD display monitor |
| 中文描述： | 轉(zhuǎn)換電腦/蘋果的視頻圖像的TFT液晶顯示屏 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 391K |
| 代理商： | STK6005 |
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STK6005
4. Write lower 8 bits, and then write higher 2 bits data into uWrGmaD register to program
a 10-bit Gamma value.
5. Go to step 4 for continuing to write the next address.
Go to step 3 for changing another address.
Go to step 2 for changing another Gamma LUT.
Go to next step to stop Gamma LUT programming.
6. Enable Gamma correlation function (set EnGamma flag to 1).
5.11 Output Dithering
The Gamma LUT outputs a 10-bit value for each color channel. This value can be dithered down to
either 8 bits for 24 bits per pixel panels, or 6-bit for 18 bits per pixel panels. Dithering works by spreading
the quantization error over neighboring pixels both spatially and temporarily. The dithering benefits and
improves the effective color depth because the humans’ eyes will tend to average neighboring pixels and a
smooth image free of contours will be perceived.
5.12 Clock System
STK6005 takes input clock (VCLK) from external ADC or video decoder chips. The input pixels are
latched on the rising edge of VCLK by default. The input phase of VCLK can be inverted by setting
SetICLK flag to 1.
The internal panel clock PCLK can be obtained either from an external source (from ExtPCLK pin) or
generated from an internal PLL. The PLL takes the external crystal oscillator input (14.3MHz) or VCLK
as clock source to synthesize the clock for panel. The clock frequency synthesized by PLL can be
programmed to support different display modes. The panel clock is output to DCLK with equal or 1/2 of
frequency of PCLK for single or dual pixel output modes respectively. The output delay and phase of
DCLK can be programmed by internal registers SetDCLK and DlyDCLK. The PLL block diagram and
control registers are depicted as follows:
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