- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374945 > STK6005 (Electronic Theatre Controls, Inc.) converting PC / Mac video images for a TFT-LCD display monitor PDF資料下載
參數(shù)資料
| 型號： | STK6005 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | converting PC / Mac video images for a TFT-LCD display monitor |
| 中文描述： | 轉(zhuǎn)換電腦/蘋果的視頻圖像的TFT液晶顯示屏 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 391K |
| 代理商： | STK6005 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
15
STK6005
HSR = horizontal input display resolution / output display resolution * 32768
VSR = vertical input display resolution / output display resolution * 32768
This chip provides 6 advanced filters to get a high quality-scaling image for requirements on different
sharpness. Set EnFilt flag to 1 to enable scaling function using the filter defined by FiltType register.
5.8 Operating Mode
STK6005 uses internal line buffers to perform the scaling function. Since there is no external frame buffer
serving as a frame rate converter, the output vertical frequency is always equal to the input vertical frequency
during normal operation. The period of PCLK should be programmed as close as the formula listed below to
avoid over-run / under-run conditions of internal line-buffers.
Period of PCLK = Period of VCLK * RateH * RateV
where
RateH = total pixels of an input line / total pixels of an output line
RateV = total input lines / total output lines
= total input display lines / total output display lines
STK6005 provides three operating modes to synchronize the input and output display timing:
1. Free-run mode:
EnSyncH {0x3D[7]} = 0
EnSyncV {0x3D[6]} = 0
In this mode, there is no timing relationship between the input and output timing. Registers PHT and
PVT control the output horizontal period and vertical period respectively. For this mode, even if no input
signal comes, the output timing can also be generated automatically. This mode is used when there is no
valid input or used for testing purpose.
2. Synchronization to Input V-Sync:
EnSyncH {0x3D[7]} = 0
EnSyncV {0x3D[6]} = 1
In this mode, the input vertical timing has impacted on the output vertical timing. The input V-Sync
leading edge will generate a locking event to lock the output display timing. Therefore, the output vertical
period will keep the same as the input vertical period. The latency between the input V-Sync leading edge
and the locking event can be programmed through registers DlyLine and DlyPxl. The output horizontal
period is set by PHT. The PVT value should be set to maximum (0x7FF) value for this mode. For the
advantage of this mode, all output horizontal periods are equal. For the disadvantage of this mode, when
some errors occur in the real output video clock (PCLK) and in the ideal output video clock (VCLK *
RateH * RateV), the buffer overrun or underrun may happen internally due to the accumulation of errors.
Back to Contents Table
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STK6005F | converting PC / Mac video images for a TFT-LCD display monitor |
| STK6103 | Metalized Polyester Film Radial Lead Capacitor; Capacitance: .22uF; Voltage: 400V; Case Size: 15.5x10.4 mm; Packaging: Bulk |
| STK6105 | DC 3-phase Brushless Motor Driver (Output Current 5A) |
| STK621-015 | SANYO INVERTER POWER HYBRID MODULE SIP Full Molded Package |
| STK621-017 | TENTATIVE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STK6005F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:converting PC / Mac video images for a TFT-LCD display monitor |
| STK6031 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:微控制器 |
| STK6031A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STK6031是一款8051單片機，64K FLASH空間，最多可支持36個IO口，有PWM和AD口，有PLCC、QFP、LQFP三種封裝。 |
| STK6032 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:基于8051的8位微控制器 |
| STK6033 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:基于8051的8位微控制器 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。