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參數(shù)資料
| 型號(hào)： | STK17TA8-W25 |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | REAL TIME CLOCK, PDIP40 |
| 封裝： | 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 285K |
| 代理商： | STK17TA8-W25 |
STK17TA8
April 2005
Document Control #ML0025 rev 1.1
7
SRAM WRITE CYCLES #1 & #2
Notes
g: If W
is low when E goes low, the outputs remain in the high-impedance state.
h: E
or W
must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1:
W Controlledh,f
SRAM WRITE CYCLE #2:
E Controlledh,f
SYMBOLS
STK17TA8-25
STK17TA8-35
STK17TA8-45
UNITS
NO.
#1
#2
Alt.
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
12
tAVAV
tWC
Write Cycle Time
25
35
45
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
25
30
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
25
30
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
12
15
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
25
30
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
ns
20
tWLQZe,g
tWZ
Write Enable to Output Disable
10
13
15
ns
21
tWHQX
tOW
Output Active after End of Write
3
ns
ADDRESS
DATA OUT
DATA IN
W
E
ADDRESS
HIGH IMPEDANCE
DATA VALID
PREVIOUS DATA
14
tELWH
19
tWHAX
17
tAVWH
18
tAVWL
13
tWLWH
15
tDVWH
16
tWHDX
20
tWLQZ
21
tWHQX
12
tAVAV
DATA OUT
DATA IN
W
E
HIGH IMPEDANCE
DATA VALID
12
tAVAV
14
tELEH
18
tAVEL
19
tEHAX
17
tAVEH
13
tWLEH
15
tDVEH
16
tEHDX
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