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參數(shù)資料
| 型號： | STK17TA8-W25 |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDIP40 |
| 封裝： | 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 285K |
| 代理商： | STK17TA8-W25 |
April 2005
Document Control #ML0025 rev 1.1
1
STK17TA8
nvTime
TM Event Data Recorder
128K x 8 AutoStore
TM nvSRAM
With Real-Time Clock
FEATURES
Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
Watchdog Timer
Clock Alarm with programmable Interrupts
Capacitor or battery backup for RTC
25ns, 35ns and 45ns Access Times
“Hands-off” Automatic STORE on Power Down
with only a small capacitor
STORE to QuantumTrap Initiated by
Software , device pin, or on Power Down
RECALL to SRAM Initiated by Software or
Power Up
Unlimited READ, WRITE and RECALL Cycles
High-reliability
o
Endurance to 1 Million Cycles
o
Retention to 100 years at 125 C
5mA Typical I
CC at 200ns Cycle Time
Single 3V +20%, -10% Operation
SSOP and DIP Packages, (ROHS compliant)
DESCRIPTION
The Simtek STK17TA8 combines a 1 Mbit nonvola-
tile static RAM with a full-featured real-time clock in
a reliable, monolithic integrated circuit. The embed-
ded nonvolatile elements incorporate Simtek’s
QuantumTrap
technology producing the world’s
most reliable nonvolatile memory. The SRAM can
be read and written an unlimited number of times,
while independent, nonvolatile data resides in the
nonvolatile elements.
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is pro-
grammable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programma-
ble Watchdog Timer for process control.
BLOCK DIAGRAM
RO
W
D
E
CO
D
E
R
IN
P
U
T
B
U
FFERS
COLUMN DEC
G
E
W
COLUMN I/O
POWER
CONTROL
HSB
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A15 – A0
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
Quantum Trap
1024 X 1024
STATIC RAM
ARRAY
1024 X 1024
STORE
RECALL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 A1 A2 A3 A4 A10 A11
VCC
VCAP
RTC
MUX
A16 – A0
X1
X2
INT
VRTCbat
VRTCcap
Figure 1. Block Diagram
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