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參數(shù)資料
| 型號： | STK17TA8-W25 |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, PDIP40 |
| 封裝： | 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 285K |
| 代理商： | STK17TA8-W25 |
STK17TA8
April 2005
Document Control #ML0025 rev 1.1
6
SRAM READ CYCLES #1 & #2
SYMBOLS
STK17TA8-25
STK17TA8-35
STK17TA8-45
NO.
#1
#2
Alt.
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
1
tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2
tAVAV
c
tAVAV
c
tRC
Read Cycle Time
25
35
45
ns
3
tAVQV
d
tAA
Address Access Time
25
35
45
ns
4
tGLQV
tOE
Output Enable to Data Valid
12
15
20
ns
5
tAXQX
d
tOH
Output Hold after Address Change
3
ns
6
tELQX
tLZ
Chip Enable to Output Active
3
ns
7
tEHQZ
e
tHZ
Chip Disable to Output Inactive
10
13
15
ns
8
tGLQX
tOLZ
Output Enable to Output Active
0
ns
9
tGHQZ
e
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICC
b
tPA
Chip Enable to Power Active
0
ns
11
tEHICC
b
tPS
Chip Disable to Power Standby
25
35
45
ns
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G
both low
e: Measured
± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlledc,d,f
SRAM READ CYCLE #2:
E Controlledc,f
DQ (DATA OUT)
ADDRESS
3
tAVQV
5
tAXQX
DATA VALID
2
tAVAV
2
tAVAV
DATA VALID
ADDRESS
DQ (DATA OUT)
ICC
STANDBY
ACTIVE
1
tELQV
6
tELQX
4
tGLQV
8
tGLQX
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ
E
G
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