
SEC ASIC
3-9
STD80/STDM80
OA22
Two 2-ORs into 2-NAND
OA22D2
Two 2-ORs into 2-NAND with 2X Drive
OA22A
2-OR and 2-NAND into 2-NAND
OA22D2A
2-OR and 2-NAND into 2-NAND with 2X Drive
OA2222
Four 2-ORs into 4-NAND
OA2222D2
Four 2-ORs into 4-NAND with 2X Drive
DL1D2
1ns Delay Cell with 2X Drive
DL1D4
1ns Delay Cell with 4X Drive
DL2D2
2ns Delay Cell with 2X Drive
DL2D4
2ns Delay Cell with 4X Drive
DL3D2
3ns Delay Cell with 2X Drive
DL3D4
3ns Delay Cell with 4X Drive
DL4D2
4ns Delay Cell with 2X Drive
DL4D4
4ns Delay Cell with 4X Drive
DL5D2
5ns Delay Cell with 2X Drive
DL5D4
5ns Delay Cell with 4X Drive
DL10D2
10ns Delay Cell with 2X Drive
DL10D4
10ns Delay Cell with 4X Drive
IV
Inverter
IVD2
Inverter with 2X Drive
IVD3
Inverter with 3X Drive
IVD4
Inverter with 4X Drive
IVD6
Inverter with 6X Drive
IVD8
Inverter with 8X Drive
IVA
Inverter with 2X P-Transistor, 1X N-Transistor
IVD2A
Inverter with 4X P-Transistor, 2X N-Transistor
IVD3A
Inverter with 6X P-Transistor, 3X N-Transistor
IVD4A
Inverter with 8X P-Transistor, 4X N-Transistor
IVCD11
1X Inverter into 1X Inverter
IVCD13
1X Inverter into 3X Inverter
IVCD22
2X Inverter into 2X Inverter
IVCD26
2X Inverter into 6X Inverter
IVCD44
4X Inverter into 4X Inverter
IVT
Inverting Tri-State Buffer with Enable High
Cell Name
Function Description
LOGIC CELLS
Cell List (Continued)