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參數(shù)資料
| 型號： | STAC9708 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | Multi-Channel AC97 Codec With Multi-Codec Option |
| 中文描述： | 多聲道AC97編解碼器與多編解碼器方案 |
| 文件頁數(shù)： | 19/56頁 |
| 文件大小： | 247K |
| 代理商： | STAC9708 |
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SigmaTel, Inc.
Preliminary
STAC9708/11
19
10/02/98
3.1.1.12 Slot 12: Reserved
Audio output frame slot 12 is reserved for modem operations and is not used by the
STAC9708/11
.
3.1.2 AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC'97 controller. As is the case for audio output frame, each AC-Link audio input frame
consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for
AC-Link protocol infrastructure.
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the
STAC9708/11
is in the "Codec Ready" state or not. If the “Codec Ready” bit is a 0, this indicates that
STAC9708/11
is not ready for normal operation. This condition is normal following the de-assertion of
power on reset, for example, while
STAC9708/11
’s voltage references settle. When the AC-Link
"Codec Ready" indicator bit is a 1, it indicates that the AC-Link and
STAC9708/11
control/status
registers are in a fully operational state. The AC'97 controller must further probe the Powerdown
Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any,
are ready.
Prior to any attempts at putting
STAC9708/11
into operation the AC'97 controller should poll the first
bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that
STAC9708/11
has become
"Codec Ready". Once the
STAC9708/11
is sampled "Codec Ready", the next 12 bit positions sampled
by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data
streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link
protocol.
Figure 8
.
STAC9708/11
Audio Input Frame
SYNC
BIT_CLK
SDATA_IN
valid
Frame
slot1
slot2
End of previous audio frame
slot(12) "0"
"0"
"0"
19
"0"
"0"
"0"
19
19
19
"0"
Data Phase
20.8 uS (48 kHZ)
Tag Phase
12.288 MHz
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
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