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參數(shù)資料
| 型號(hào)： | ST72621J2B1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 130/136頁(yè) |
| 文件大?。?/td> | 2475K |
| 代理商： | ST72621J2B1 |
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.7.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRMSB register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/2
1: fADC = fCPU/4
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software or by hard-
ware after the end of a one shot conversion.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = ITE Interrupt Enable
This bit is set and cleared by software.
0: EOC Interrupt disabled
1: EOC Interrupt enabled
Bit 3 = ONESHOT One Shot Conversion Selection
This bit is set and cleared by software.
0: Continuous conversion mode
1: One Shot conversion mode
Bit 2:0 = CS[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER (ADCDRMSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
This register contains the MSB of the converted
analog value.
DATA REGISTER (ADCDRLSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
This register contains the LSB of the converted an-
alog value.
70
EOC
SPEED ADON
ITE
ONE
SHOT
CS2
CS1
CS0
Channel*
CS2
CS1
CS0
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
70
D9
D8
D7
D6
D5
D4
D3
D2
70
00
D1
D0
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