參數(shù)資料
型號: ST52514K3
英文描述: IC MAX 7000 CPLD 256 100-TQFP
中文描述: 8位重癥監(jiān)護(hù)病房,10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù): 92/106頁
文件大?。?/td> 1355K
代理商: ST52514K3
Acknowledge may be enabled and disabled via
software.
The I2C interface address and/or general call
address can be selected via software.
The speed of the I2C interface may be selected
between Standard (0-100KHz) and Fast I2C (100-
400KHz).
13.3.3 SDA/SCL Line Control.
Transmitter mode: the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I2C bus mode.
When the I2C cell is enabled, the SDA and SCL
pins must be configured as floating open-drain I/O.
The value of the external pull-up resistance used
depends on the application.
13.4 Functional Description
By default the I2C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First, the interface frequency must be configured
using
the
related
bits
of
the
Configuration
Registers.
13.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Figure 13.2 I2C Interface Block Diagram
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL REGISTER (I2C_CCR)
STATUS REGISTER 1 (I2C_SR1)
CONTROL REGISTER (I2C_CR)
SDA
SCL
CONTROL LOGIC
STATUS REGISTER 2 (I2C_SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL
SDA
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