參數(shù)資料
型號： ST52514K3
英文描述： IC MAX 7000 CPLD 256 100-TQFP
中文描述： 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存
文件頁數(shù)： 50/106頁
文件大?。?/td> 1355K
代理商： ST52514K3
48/106
6.6.2 Option Bytes.
Clock Mode (OSC_CR)
Option Byte 0 (00h)
Reset Value: 0000 0000 (00h)
Bit 7-4: Not used
Bit 3-2: OSPR1-0 Internal Oscillator Prescaler
00: Internal Clock frequency = 10 MHz
01: Internal Clock frequency = 5 MHz
10: Internal Clock frequency = 2.5 MHz
11: Internal Clock frequency = 1.25 MHz
Bit 1-0: CKMOD1-0 Clock Mode
00: Internal Oscillator
01: External Clock or quartz
1x: External RC oscillator
External Clock Parameters (CLK_SET)
Option Byte 1 (01h)
Reset Value: 0000 0000 (00h)
Bit 7-3: Not Used
Bit 2-0: CKPAR2-0 Oscillator Gains
These three bits enable/disable the loop
gains when a external clock or quartz are
used
for
generating
the
clock.
The
following table describes the possible
configuration options. Table 6.2 illustrates
the recommended values for the most
common frequencies used, time to start the
oscillations and the settling time to have a
duty cycle of 40%-60% (at steady state it is
50%).
Warning: If an External Clock is used instead of a
quartz or ceramic resonator, it is recommended
that no gain be enabled (CKPAR2-0=000) in order
to lower the current consumption.
70
-
OSPR1
OSPR0 CKMOD1 CKMOD0
70
-
CKPAR2 CKPAR1 CKPAR0
CKPAR2-0
Enabled Gain Stages
000
No Gains (External Clock Mode)
001
1 gain stage enabled
010
2 gain stage enabled
011
3 gain stage enabled
100
4 gain stage enabled
101
5 gain stage enabled
110
6 gain stage enabled
111
7 gain stage enabled
Table 6.2 Recommended Gains for the most common frequencies
Frequency
Recommend
Gain Stages (1)
CKPAR2-0
Oscillation
Start Times (2)
Settling Times for
60% duty-cycle (2)
External Clock
0
000
-
1 MHz
1
001
280
150
5 MHz
2
010
20.4
60
10 MHz
4
100
9.2
11
16 MHz
5
101
187
50
20 MHz
7
111
55
18
(1) The recommended values have been chosen to have the best trade off between start time and current
consumption. Higher gains give shorter Start times; lower gains give less current consumption.
(2) Indicative values by design at 25° Celsius, VDD=1.8 V. Not Tested in production.
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