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| 型號： | ST52514K3 |
| 英文描述： | IC MAX 7000 CPLD 256 100-TQFP |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 86/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52514K3 |
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Recognition of a STOP condition transfers data
received
from
the
Recovery
Buffer
to
the
SCDR_RX buffer, adding the eventual ninth data
bit. After this operation, RXF flag (bit 5) of SCI
Status Input Register is set to logic level 1. The
Control Unit reads data from the SCDR_RX buffer
(in read-only mode) by reading the SCI_IN Input
Register (address 36 024h) with the LDRI
instruction and provides a reset at logic level 0 to
the RXF flag.
If data of the Recovery Buffer is ready to be
transferred into the SCDR_RX buffer, but the
previous one has not been read by the Core, an
OVERRUN Error takes place: the SCI Status
Register flag OVERR (bit 4) indicates the error
condition. In this case, information that is stored in
the SCDR_RX buffer is not altered, but the one
that has caused the OVERRUN error can be
overwritten by new data deriving from the serial
data line.
12.1.1 Recovery Buffer Block .
This block is structured as a synchronized finite
state machine on the CLOCK_RX signal.
When the Recovery Buffer Block is in IDLE state it
waits for the reception of the correct 1 and 0
sequence representing START.
Recognition takes place by sampling the input RX
at CLOCK_RX frequency, which has a frequency
that is 16 times higher than CLOCK_TX. For this
reason, while the external transmitter sends a
single bit, the Recovery Buffer Block samples 16
states (from SAMPLE1 to SAMPLE16).
Analysis of the RX input signal is carried out by
checking three samples for each bit received.
If these three samples are not equal, then the
noise error flag, NSERR (bit 7), of SCI Status
Register is set to 1 and the data received value will
be the one assumed by the majority of the
samples.
The procedure described above, allows SCI not to
becomes IDLE, because of a limited noise due to
an erroneous sampling, the transmission is
recognized as correct and the noise flag error is
set.
At the end of the cycle of the reception of a bit, the
Recovery Buffer Block will repeat the same steps 9
times: one step for each bit received, plus one for
the stop acquisition (10 times in case of 9-bit data,
double stop or parity check).
At the end of data reception the Recovery Buffer
Block will supply information about eventual frame
errors by setting the 1 FRERR flag (bit 6) of the SCI
Status Register to 1.
A frame error can occur if the parity check hasn’t
been successfully achieved or if the STOP bit has
not been detected.
If
the
Recovery
Buffer
Block
receives
10
consecutive bits at logic level 0, a Line Break
condition occurs, the related Interrupt Request is
sent and the BRK flag in the SCI Status Register is
set.
12.1.2 SCDR_RX Block.
It is a finite state machine synchronized with the
clock master signal, CKM.
The SCDR_RX block waits for the signal of
complete reception from the Recovery Buffer in
order to load the word received. Moreover, the
SCDR_RX block loads the values of FRERR and
NSERR flag bits of the Status Register, and sets
the RXF flag to 1.
By using the LDRI instruction data is transferred to
Register File and RXF flag is reset to 0, to indicate
that the SCDR_RX block is empty.
If new data arrives before the previous one has
been transferred to Register File, the overrun error
occurs and the OVERR flag of Status Register is
set to 1.
Figure 12.3 SCI Status Register
D7 D6 D5 D4 D3 D2 D1 D0
S C I_ S T A T U S In p u t R egis ter 37
T X E N D
- E N D T R ANSM IS SIO N
T X E M
- T RA NS M IS S IO N DA T A RE GIS T E R E M P T Y
R8
- R EC E IVED N IN T H BIT
NSER R
- NO IS E ERR O R
BRK
O V ER R
- OVER RU N ER RO R
RX F
- REC E IVE D A T A R E GIST ER F U L L
F R ER R
- F R AM E ER RO R
- L IN E BR EA K
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